1Freescale i.MX DRM master device
2================================
3
4The freescale i.MX DRM master device is a virtual device needed to list all
5IPU or other display interface nodes that comprise the graphics subsystem.
6
7Required properties:
8- compatible: Should be "fsl,imx-display-subsystem"
9- ports: Should contain a list of phandles pointing to display interface ports
10  of IPU devices
11
12example:
13
14display-subsystem {
15	compatible = "fsl,display-subsystem";
16	ports = <&ipu_di0>;
17};
18
19
20Freescale i.MX IPUv3
21====================
22
23Required properties:
24- compatible: Should be "fsl,<chip>-ipu"
25- reg: should be register base and length as documented in the
26  datasheet
27- interrupts: Should contain sync interrupt and error interrupt,
28  in this order.
29- resets: phandle pointing to the system reset controller and
30          reset line index, see reset/fsl,imx-src.txt for details
31Optional properties:
32- port@[0-3]: Port nodes with endpoint definitions as defined in
33  Documentation/devicetree/bindings/media/video-interfaces.txt.
34  Ports 0 and 1 should correspond to CSI0 and CSI1,
35  ports 2 and 3 should correspond to DI0 and DI1, respectively.
36
37example:
38
39ipu: ipu@18000000 {
40	#address-cells = <1>;
41	#size-cells = <0>;
42	compatible = "fsl,imx53-ipu";
43	reg = <0x18000000 0x080000000>;
44	interrupts = <11 10>;
45	resets = <&src 2>;
46
47	ipu_di0: port@2 {
48		reg = <2>;
49
50		ipu_di0_disp0: endpoint {
51			remote-endpoint = <&display_in>;
52		};
53	};
54};
55
56Freescale i.MX PRE (Prefetch Resolve Engine)
57============================================
58
59Required properties:
60- compatible: should be "fsl,imx6qp-pre"
61- reg: should be register base and length as documented in the
62  datasheet
63- clocks : phandle to the PRE axi clock input, as described
64  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
65  Documentation/devicetree/bindings/clock/imx6q-clock.txt.
66- clock-names: should be "axi"
67- interrupts: should contain the PRE interrupt
68- fsl,iram: phandle pointing to the mmio-sram device node, that should be
69  used for the PRE SRAM double buffer.
70
71example:
72
73pre@21c8000 {
74	compatible = "fsl,imx6qp-pre";
75	reg = <0x021c8000 0x1000>;
76	interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
77	clocks = <&clks IMX6QDL_CLK_PRE0>;
78	clock-names = "axi";
79	fsl,iram = <&ocram2>;
80};
81
82Parallel display support
83========================
84
85Required properties:
86- compatible: Should be "fsl,imx-parallel-display"
87Optional properties:
88- interface_pix_fmt: How this display is connected to the
89  display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
90  and "lvds666".
91- edid: verbatim EDID data block describing attached display.
92- ddc: phandle describing the i2c bus handling the display data
93  channel
94- port@[0-1]: Port nodes with endpoint definitions as defined in
95  Documentation/devicetree/bindings/media/video-interfaces.txt.
96  Port 0 is the input port connected to the IPU display interface,
97  port 1 is the output port connected to a panel.
98
99example:
100
101display@di0 {
102	compatible = "fsl,imx-parallel-display";
103	edid = [edid-data];
104	interface-pix-fmt = "rgb24";
105
106	port@0 {
107		reg = <0>;
108
109		display_in: endpoint {
110			remote-endpoint = <&ipu_di0_disp0>;
111		};
112	};
113
114	port@1 {
115		reg = <1>;
116
117		display_out: endpoint {
118			remote-endpoint = <&panel_in>;
119		};
120	};
121};
122
123panel {
124	...
125
126	port {
127		panel_in: endpoint {
128			remote-endpoint = <&display_out>;
129		};
130	};
131};
132