1Device-Tree bindings for hisilicon ADE display controller driver
2
3ADE (Advanced Display Engine) is the display controller which grab image
4data from memory, do composition, do post image processing, generate RGB
5timing stream and transfer to DSI.
6
7Required properties:
8- compatible: value should be "hisilicon,hi6220-ade".
9- reg: physical base address and length of the ADE controller's registers.
10- hisilicon,noc-syscon: ADE NOC QoS syscon.
11- resets: The ADE reset controller node.
12- interrupt: the ldi vblank interrupt number used.
13- clocks: a list of phandle + clock-specifier pairs, one for each entry
14  in clock-names.
15- clock-names: should contain:
16  "clk_ade_core" for the ADE core clock.
17  "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
18  jpeg codec.
19  "clk_ade_pix" for the ADE pixel clock.
20- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
21  phandle + clock-specifier pairs.
22- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
23  The rate of "clk_ade_core" could be "360000000" or "180000000";
24  The rate of "clk_codec_jpeg" could be or less than "1440000000".
25  These rate values could be configured according to performance and power
26  consumption.
27- port: the output port. This contains one endpoint subnode, with its
28  remote-endpoint set to the phandle of the connected DSI input endpoint.
29  See Documentation/devicetree/bindings/graph.txt for more device graph info.
30
31Optional properties:
32- dma-coherent: Present if dma operations are coherent.
33
34
35A example of HiKey board hi6220 SoC specific DT entry:
36Example:
37
38	ade: ade@f4100000 {
39		compatible = "hisilicon,hi6220-ade";
40		reg = <0x0 0xf4100000 0x0 0x7800>;
41		reg-names = "ade_base";
42		hisilicon,noc-syscon = <&medianoc_ade>;
43		resets = <&media_ctrl MEDIA_ADE>;
44		interrupts = <0 115 4>; /* ldi interrupt */
45
46		clocks = <&media_ctrl HI6220_ADE_CORE>,
47			 <&media_ctrl HI6220_CODEC_JPEG>,
48			 <&media_ctrl HI6220_ADE_PIX_SRC>;
49		/*clock name*/
50		clock-names  = "clk_ade_core",
51			       "clk_codec_jpeg",
52			       "clk_ade_pix";
53
54		assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
55			<&media_ctrl HI6220_CODEC_JPEG>;
56		assigned-clock-rates = <360000000>, <288000000>;
57		dma-coherent;
58
59		port {
60			ade_out: endpoint {
61				remote-endpoint = <&dsi_in>;
62			};
63		};
64	};
65