1284aabb0SXinliang LiuDevice-Tree bindings for DesignWare DSI Host Controller v1.20a driver 2284aabb0SXinliang Liu 3284aabb0SXinliang LiuA DSI Host Controller resides in the middle of display controller and external 4284aabb0SXinliang LiuHDMI converter or panel. 5284aabb0SXinliang Liu 6284aabb0SXinliang LiuRequired properties: 7284aabb0SXinliang Liu- compatible: value should be "hisilicon,hi6220-dsi". 8284aabb0SXinliang Liu- reg: physical base address and length of dsi controller's registers. 9284aabb0SXinliang Liu- clocks: contains APB clock phandle + clock-specifier pair. 10284aabb0SXinliang Liu- clock-names: should be "pclk". 11284aabb0SXinliang Liu- ports: contains DSI controller input and output sub port. 12284aabb0SXinliang Liu The input port connects to ADE output port with the reg value "0". 13284aabb0SXinliang Liu The output port with the reg value "1", it could connect to panel or 14284aabb0SXinliang Liu any other bridge endpoints. 15284aabb0SXinliang Liu See Documentation/devicetree/bindings/graph.txt for more device graph info. 16284aabb0SXinliang Liu 17284aabb0SXinliang LiuA example of HiKey board hi6220 SoC and board specific DT entry: 18284aabb0SXinliang LiuExample: 19284aabb0SXinliang Liu 20284aabb0SXinliang LiuSoC specific: 21284aabb0SXinliang Liu dsi: dsi@f4107800 { 22284aabb0SXinliang Liu compatible = "hisilicon,hi6220-dsi"; 23284aabb0SXinliang Liu reg = <0x0 0xf4107800 0x0 0x100>; 24284aabb0SXinliang Liu clocks = <&media_ctrl HI6220_DSI_PCLK>; 25284aabb0SXinliang Liu clock-names = "pclk"; 26284aabb0SXinliang Liu status = "disabled"; 27284aabb0SXinliang Liu 28284aabb0SXinliang Liu ports { 29284aabb0SXinliang Liu #address-cells = <1>; 30284aabb0SXinliang Liu #size-cells = <0>; 31284aabb0SXinliang Liu 32284aabb0SXinliang Liu /* 0 for input port */ 33284aabb0SXinliang Liu port@0 { 34284aabb0SXinliang Liu reg = <0>; 35284aabb0SXinliang Liu dsi_in: endpoint { 36284aabb0SXinliang Liu remote-endpoint = <&ade_out>; 37284aabb0SXinliang Liu }; 38284aabb0SXinliang Liu }; 39284aabb0SXinliang Liu }; 40284aabb0SXinliang Liu }; 41284aabb0SXinliang Liu 42284aabb0SXinliang Liu 43284aabb0SXinliang LiuBoard specific: 44284aabb0SXinliang Liu &dsi { 45284aabb0SXinliang Liu status = "ok"; 46284aabb0SXinliang Liu 47284aabb0SXinliang Liu ports { 48284aabb0SXinliang Liu /* 1 for output port */ 49284aabb0SXinliang Liu port@1 { 50284aabb0SXinliang Liu reg = <1>; 51284aabb0SXinliang Liu 52284aabb0SXinliang Liu dsi_out0: endpoint@0 { 53284aabb0SXinliang Liu remote-endpoint = <&adv7533_in>; 54284aabb0SXinliang Liu }; 55284aabb0SXinliang Liu }; 56284aabb0SXinliang Liu }; 57284aabb0SXinliang Liu }; 58284aabb0SXinliang Liu 59284aabb0SXinliang Liu &i2c2 { 60284aabb0SXinliang Liu ... 61284aabb0SXinliang Liu 62284aabb0SXinliang Liu adv7533: adv7533@39 { 63284aabb0SXinliang Liu ... 64284aabb0SXinliang Liu 65284aabb0SXinliang Liu port { 66284aabb0SXinliang Liu adv7533_in: endpoint { 67284aabb0SXinliang Liu remote-endpoint = <&dsi_out0>; 68284aabb0SXinliang Liu }; 69284aabb0SXinliang Liu }; 70284aabb0SXinliang Liu }; 71284aabb0SXinliang Liu }; 72284aabb0SXinliang Liu 73