1efdbd734SRob HerringDevice Tree bindings for Freescale DCU DRM Driver
2efdbd734SRob Herring
3efdbd734SRob HerringRequired properties:
4efdbd734SRob Herring- compatible:		Should be one of
5efdbd734SRob Herring	* "fsl,ls1021a-dcu".
6efdbd734SRob Herring	* "fsl,vf610-dcu".
7efdbd734SRob Herring
8efdbd734SRob Herring- reg:			Address and length of the register set for dcu.
9f93500f4SStefan Agner- clocks:		Handle to "dcu" and "pix" clock (in the order below)
10f93500f4SStefan Agner			This can be the same clock (e.g. LS1021a)
11f93500f4SStefan Agner			See ../clocks/clock-bindings.txt for details.
12f93500f4SStefan Agner- clock-names:		Should be "dcu" and "pix"
13f93500f4SStefan Agner			See ../clocks/clock-bindings.txt for details.
14efdbd734SRob Herring- big-endian		Boolean property, LS1021A DCU registers are big-endian.
15924591b1SMeng Yi- port			Video port for the panel output
16efdbd734SRob Herring
17fb127b79SStefan AgnerOptional properties:
18fb127b79SStefan Agner- fsl,tcon:		The phandle to the timing controller node.
19fb127b79SStefan Agner
20efdbd734SRob HerringExamples:
21efdbd734SRob Herringdcu: dcu@2ce0000 {
22efdbd734SRob Herring	compatible = "fsl,ls1021a-dcu";
23efdbd734SRob Herring	reg = <0x0 0x2ce0000 0x0 0x10000>;
24f93500f4SStefan Agner	clocks = <&platform_clk 0>, <&platform_clk 0>;
25f93500f4SStefan Agner	clock-names = "dcu", "pix";
26efdbd734SRob Herring	big-endian;
27fb127b79SStefan Agner	fsl,tcon = <&tcon>;
28924591b1SMeng Yi
29924591b1SMeng Yi	port {
30924591b1SMeng Yi		dcu_out: endpoint {
31924591b1SMeng Yi			remote-endpoint = <&panel_out>;
32924591b1SMeng Yi	     };
33924591b1SMeng Yi	};
34efdbd734SRob Herring};
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