1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SN65DSI86 DSI to eDP bridge chip
8
9maintainers:
10  - Sandeep Panda <spanda@codeaurora.org>
11
12description: |
13  The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
14  https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
15
16properties:
17  compatible:
18    const: ti,sn65dsi86
19
20  reg:
21    const: 0x2d
22
23  enable-gpios:
24    maxItems: 1
25    description: GPIO specifier for bridge_en pin (active high).
26
27  suspend-gpios:
28    maxItems: 1
29    description: GPIO specifier for GPIO1 pin on bridge (active low).
30
31  no-hpd:
32    type: boolean
33    description:
34      Set if the HPD line on the bridge isn't hooked up to anything or is
35      otherwise unusable.
36
37  vccio-supply:
38    description: A 1.8V supply that powers the digital IOs.
39
40  vpll-supply:
41    description: A 1.8V supply that powers the DisplayPort PLL.
42
43  vcca-supply:
44    description: A 1.2V supply that powers the analog circuits.
45
46  vcc-supply:
47    description: A 1.2V supply that powers the digital core.
48
49  interrupts:
50    maxItems: 1
51
52  clocks:
53    maxItems: 1
54    description:
55      Clock specifier for input reference clock. The reference clock rate must
56      be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
57
58  clock-names:
59    const: refclk
60
61  gpio-controller: true
62  '#gpio-cells':
63    const: 2
64    description:
65      First cell is pin number, second cell is flags.  GPIO pin numbers are
66      1-based to match the datasheet.  See ../../gpio/gpio.txt for more
67      information.
68
69  '#pwm-cells':
70    const: 1
71    description: See ../../pwm/pwm.yaml for description of the cell formats.
72
73  ports:
74    type: object
75    additionalProperties: false
76
77    properties:
78      "#address-cells":
79        const: 1
80
81      "#size-cells":
82        const: 0
83
84      port@0:
85        type: object
86        additionalProperties: false
87
88        description:
89          Video port for MIPI DSI input
90
91        properties:
92          reg:
93            const: 0
94
95          endpoint:
96            type: object
97            additionalProperties: false
98            properties:
99              remote-endpoint: true
100
101        required:
102          - reg
103
104      port@1:
105        type: object
106        additionalProperties: false
107
108        description:
109          Video port for eDP output (panel or connector).
110
111        properties:
112          reg:
113            const: 1
114
115          endpoint:
116            type: object
117            additionalProperties: false
118
119            properties:
120              remote-endpoint: true
121
122              data-lanes:
123                oneOf:
124                  - minItems: 1
125                    maxItems: 1
126                    uniqueItems: true
127                    items:
128                      enum:
129                        - 0
130                        - 1
131                    description:
132                      If you have 1 logical lane the bridge supports routing
133                      to either port 0 or port 1.  Port 0 is suggested.
134                      See ../../media/video-interface.txt for details.
135
136                  - minItems: 2
137                    maxItems: 2
138                    uniqueItems: true
139                    items:
140                      enum:
141                        - 0
142                        - 1
143                    description:
144                      If you have 2 logical lanes the bridge supports
145                      reordering but only on physical ports 0 and 1.
146                      See ../../media/video-interface.txt for details.
147
148                  - minItems: 4
149                    maxItems: 4
150                    uniqueItems: true
151                    items:
152                      enum:
153                        - 0
154                        - 1
155                        - 2
156                        - 3
157                    description:
158                      If you have 4 logical lanes the bridge supports
159                      reordering in any way.
160                      See ../../media/video-interface.txt for details.
161
162              lane-polarities:
163                minItems: 1
164                maxItems: 4
165                items:
166                  enum:
167                    - 0
168                    - 1
169                description: See ../../media/video-interface.txt
170
171            dependencies:
172              lane-polarities: [data-lanes]
173
174        required:
175          - reg
176
177    required:
178      - "#address-cells"
179      - "#size-cells"
180      - port@0
181      - port@1
182
183required:
184  - compatible
185  - reg
186  - enable-gpios
187  - vccio-supply
188  - vpll-supply
189  - vcca-supply
190  - vcc-supply
191  - ports
192
193additionalProperties: false
194
195examples:
196  - |
197    #include <dt-bindings/clock/qcom,rpmh.h>
198    #include <dt-bindings/gpio/gpio.h>
199    #include <dt-bindings/interrupt-controller/irq.h>
200
201    i2c {
202      #address-cells = <1>;
203      #size-cells = <0>;
204
205      bridge@2d {
206        compatible = "ti,sn65dsi86";
207        reg = <0x2d>;
208
209        interrupt-parent = <&tlmm>;
210        interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
211
212        enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
213
214        vpll-supply = <&src_pp1800_s4a>;
215        vccio-supply = <&src_pp1800_s4a>;
216        vcca-supply = <&src_pp1200_l2a>;
217        vcc-supply = <&src_pp1200_l2a>;
218
219        clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
220        clock-names = "refclk";
221
222        no-hpd;
223
224        ports {
225          #address-cells = <1>;
226          #size-cells = <0>;
227
228          port@0 {
229            reg = <0>;
230            endpoint {
231              remote-endpoint = <&dsi0_out>;
232            };
233          };
234
235          port@1 {
236            reg = <1>;
237            endpoint {
238              remote-endpoint = <&panel_in_edp>;
239            };
240          };
241        };
242      };
243    };
244  - |
245    #include <dt-bindings/clock/qcom,rpmh.h>
246    #include <dt-bindings/gpio/gpio.h>
247    #include <dt-bindings/interrupt-controller/irq.h>
248
249    i2c {
250      #address-cells = <1>;
251      #size-cells = <0>;
252
253      bridge@2d {
254        compatible = "ti,sn65dsi86";
255        reg = <0x2d>;
256
257        enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
258        suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>;
259
260        interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
261
262        vccio-supply = <&pm8916_l17>;
263        vcca-supply = <&pm8916_l6>;
264        vpll-supply = <&pm8916_l17>;
265        vcc-supply = <&pm8916_l6>;
266
267        clock-names = "refclk";
268        clocks = <&input_refclk>;
269
270        ports {
271          #address-cells = <1>;
272          #size-cells = <0>;
273
274          port@0 {
275            reg = <0>;
276
277            edp_bridge_in: endpoint {
278              remote-endpoint = <&dsi_out>;
279            };
280          };
281
282          port@1 {
283            reg = <1>;
284
285            edp_bridge_out: endpoint {
286              data-lanes = <2 1 3 0>;
287              lane-polarities = <0 1 0 1>;
288              remote-endpoint = <&edp_panel_in>;
289            };
290          };
291        };
292      };
293    };
294