1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung MIPI DSIM bridge controller
8
9maintainers:
10  - Inki Dae <inki.dae@samsung.com>
11  - Jagan Teki <jagan@amarulasolutions.com>
12  - Marek Szyprowski <m.szyprowski@samsung.com>
13
14description: |
15  Samsung MIPI DSIM bridge controller can be found it on Exynos
16  and i.MX8M Mini/Nano/Plus SoC's.
17
18properties:
19  compatible:
20    oneOf:
21      - enum:
22          - samsung,exynos3250-mipi-dsi
23          - samsung,exynos4210-mipi-dsi
24          - samsung,exynos5410-mipi-dsi
25          - samsung,exynos5422-mipi-dsi
26          - samsung,exynos5433-mipi-dsi
27          - fsl,imx8mm-mipi-dsim
28          - fsl,imx8mp-mipi-dsim
29      - items:
30          - const: fsl,imx8mn-mipi-dsim
31          - const: fsl,imx8mm-mipi-dsim
32
33  reg:
34    maxItems: 1
35
36  interrupts:
37    maxItems: 1
38
39  '#address-cells':
40    const: 1
41
42  '#size-cells':
43    const: 0
44
45  clocks:
46    minItems: 2
47    maxItems: 5
48
49  clock-names:
50    minItems: 2
51    maxItems: 5
52
53  samsung,phy-type:
54    $ref: /schemas/types.yaml#/definitions/uint32
55    description: phandle to the samsung phy-type
56
57  power-domains:
58    maxItems: 1
59
60  samsung,power-domain:
61    $ref: /schemas/types.yaml#/definitions/phandle
62    description: phandle to the associated samsung power domain
63
64  vddcore-supply:
65    description: MIPI DSIM Core voltage supply (e.g. 1.1V)
66
67  vddio-supply:
68    description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
69
70  samsung,burst-clock-frequency:
71    $ref: /schemas/types.yaml#/definitions/uint32
72    description:
73      DSIM high speed burst mode frequency.
74
75  samsung,esc-clock-frequency:
76    $ref: /schemas/types.yaml#/definitions/uint32
77    description:
78      DSIM escape mode frequency.
79
80  samsung,pll-clock-frequency:
81    $ref: /schemas/types.yaml#/definitions/uint32
82    description:
83      DSIM oscillator clock frequency.
84
85  phys:
86    maxItems: 1
87
88  phy-names:
89    const: dsim
90
91  ports:
92    $ref: /schemas/graph.yaml#/properties/ports
93
94    properties:
95      port@0:
96        $ref: /schemas/graph.yaml#/properties/port
97        description:
98          Input port node to receive pixel data from the
99          display controller. Exactly one endpoint must be
100          specified.
101
102      port@1:
103        $ref: /schemas/graph.yaml#/properties/port
104        description:
105          DSI output port node to the panel or the next bridge
106          in the chain.
107
108        properties:
109          endpoint:
110            $ref: /schemas/media/video-interfaces.yaml#
111            unevaluatedProperties: false
112
113            properties:
114              data-lanes:
115                minItems: 1
116                maxItems: 4
117                uniqueItems: true
118                items:
119                  enum: [ 1, 2, 3, 4 ]
120
121              lane-polarities:
122                minItems: 1
123                maxItems: 5
124                description:
125                  The Samsung MIPI DSI IP requires that all the data lanes have
126                  the same polarity.
127
128            dependencies:
129              lane-polarities: [data-lanes]
130
131required:
132  - clock-names
133  - clocks
134  - compatible
135  - interrupts
136  - reg
137  - samsung,burst-clock-frequency
138  - samsung,esc-clock-frequency
139  - samsung,pll-clock-frequency
140
141allOf:
142  - $ref: ../dsi-controller.yaml#
143  - if:
144      properties:
145        compatible:
146          contains:
147            const: samsung,exynos5433-mipi-dsi
148
149    then:
150      properties:
151        clocks:
152          minItems: 5
153
154        clock-names:
155          items:
156            - const: bus_clk
157            - const: phyclk_mipidphy0_bitclkdiv8
158            - const: phyclk_mipidphy0_rxclkesc0
159            - const: sclk_rgb_vclk_to_dsim0
160            - const: sclk_mipi
161
162        ports:
163          required:
164            - port@0
165
166      required:
167        - ports
168        - vddcore-supply
169        - vddio-supply
170
171  - if:
172      properties:
173        compatible:
174          contains:
175            const: samsung,exynos5410-mipi-dsi
176
177    then:
178      properties:
179        clocks:
180          minItems: 2
181
182        clock-names:
183          items:
184            - const: bus_clk
185            - const: pll_clk
186
187      required:
188        - vddcore-supply
189        - vddio-supply
190
191  - if:
192      properties:
193        compatible:
194          contains:
195            const: samsung,exynos4210-mipi-dsi
196
197    then:
198      properties:
199        clocks:
200          minItems: 2
201
202        clock-names:
203          items:
204            - const: bus_clk
205            - const: sclk_mipi
206
207      required:
208        - vddcore-supply
209        - vddio-supply
210
211  - if:
212      properties:
213        compatible:
214          contains:
215            const: samsung,exynos3250-mipi-dsi
216
217    then:
218      properties:
219        clocks:
220          minItems: 2
221
222        clock-names:
223          items:
224            - const: bus_clk
225            - const: pll_clk
226
227      required:
228        - vddcore-supply
229        - vddio-supply
230        - samsung,phy-type
231
232additionalProperties:
233  type: object
234
235examples:
236  - |
237    #include <dt-bindings/clock/exynos5433.h>
238    #include <dt-bindings/gpio/gpio.h>
239    #include <dt-bindings/interrupt-controller/arm-gic.h>
240
241    dsi@13900000 {
242       compatible = "samsung,exynos5433-mipi-dsi";
243       reg = <0x13900000 0xC0>;
244       interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
245       phys = <&mipi_phy 1>;
246       phy-names = "dsim";
247       clocks = <&cmu_disp CLK_PCLK_DSIM0>,
248                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
249                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
250                <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
251                <&cmu_disp CLK_SCLK_DSIM0>;
252       clock-names = "bus_clk",
253                     "phyclk_mipidphy0_bitclkdiv8",
254                     "phyclk_mipidphy0_rxclkesc0",
255                     "sclk_rgb_vclk_to_dsim0",
256                     "sclk_mipi";
257       power-domains = <&pd_disp>;
258       vddcore-supply = <&ldo6_reg>;
259       vddio-supply = <&ldo7_reg>;
260       samsung,burst-clock-frequency = <512000000>;
261       samsung,esc-clock-frequency = <16000000>;
262       samsung,pll-clock-frequency = <24000000>;
263       pinctrl-names = "default";
264       pinctrl-0 = <&te_irq>;
265
266       ports {
267          #address-cells = <1>;
268          #size-cells = <0>;
269
270          port@0 {
271             reg = <0>;
272
273             dsi_to_mic: endpoint {
274                remote-endpoint = <&mic_to_dsi>;
275             };
276          };
277       };
278    };
279