1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung MIPI DSIM bridge controller
8
9maintainers:
10  - Inki Dae <inki.dae@samsung.com>
11  - Jagan Teki <jagan@amarulasolutions.com>
12  - Marek Szyprowski <m.szyprowski@samsung.com>
13
14description: |
15  Samsung MIPI DSIM bridge controller can be found it on Exynos
16  and i.MX8M Mini/Nano/Plus SoC's.
17
18properties:
19  compatible:
20    oneOf:
21      - enum:
22          - samsung,exynos3250-mipi-dsi
23          - samsung,exynos4210-mipi-dsi
24          - samsung,exynos5410-mipi-dsi
25          - samsung,exynos5422-mipi-dsi
26          - samsung,exynos5433-mipi-dsi
27          - fsl,imx8mm-mipi-dsim
28          - fsl,imx8mp-mipi-dsim
29      - items:
30          - const: fsl,imx8mn-mipi-dsim
31          - const: fsl,imx8mm-mipi-dsim
32
33  reg:
34    maxItems: 1
35
36  interrupts:
37    maxItems: 1
38
39  '#address-cells':
40    const: 1
41
42  '#size-cells':
43    const: 0
44
45  clocks:
46    minItems: 2
47    maxItems: 5
48
49  clock-names:
50    minItems: 2
51    maxItems: 5
52
53  samsung,phy-type:
54    $ref: /schemas/types.yaml#/definitions/uint32
55    description: phandle to the samsung phy-type
56
57  power-domains:
58    maxItems: 1
59
60  samsung,power-domain:
61    $ref: /schemas/types.yaml#/definitions/phandle
62    description: phandle to the associated samsung power domain
63
64  vddcore-supply:
65    description: MIPI DSIM Core voltage supply (e.g. 1.1V)
66
67  vddio-supply:
68    description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
69
70  samsung,burst-clock-frequency:
71    $ref: /schemas/types.yaml#/definitions/uint32
72    description:
73      DSIM high speed burst mode frequency when connected to devices
74      that support burst mode. If absent, the driver will use the pixel
75      clock from the attached device or bridge.
76
77  samsung,esc-clock-frequency:
78    $ref: /schemas/types.yaml#/definitions/uint32
79    description:
80      DSIM escape mode frequency.
81
82  samsung,pll-clock-frequency:
83    $ref: /schemas/types.yaml#/definitions/uint32
84    description:
85      DSIM oscillator clock frequency. If absent, the driver will
86      use the clock frequency of sclk_mipi.
87
88  phys:
89    maxItems: 1
90
91  phy-names:
92    const: dsim
93
94  ports:
95    $ref: /schemas/graph.yaml#/properties/ports
96
97    properties:
98      port@0:
99        $ref: /schemas/graph.yaml#/properties/port
100        description:
101          Input port node to receive pixel data from the
102          display controller. Exactly one endpoint must be
103          specified.
104
105      port@1:
106        $ref: /schemas/graph.yaml#/properties/port
107        description:
108          DSI output port node to the panel or the next bridge
109          in the chain.
110
111        properties:
112          endpoint:
113            $ref: /schemas/media/video-interfaces.yaml#
114            unevaluatedProperties: false
115
116            properties:
117              data-lanes:
118                minItems: 1
119                maxItems: 4
120                uniqueItems: true
121                items:
122                  enum: [ 1, 2, 3, 4 ]
123
124              lane-polarities:
125                minItems: 1
126                maxItems: 5
127                description:
128                  The Samsung MIPI DSI IP requires that all the data lanes have
129                  the same polarity.
130
131            dependencies:
132              lane-polarities: [data-lanes]
133
134required:
135  - clock-names
136  - clocks
137  - compatible
138  - interrupts
139  - reg
140  - samsung,esc-clock-frequency
141
142allOf:
143  - $ref: ../dsi-controller.yaml#
144  - if:
145      properties:
146        compatible:
147          contains:
148            const: samsung,exynos5433-mipi-dsi
149
150    then:
151      properties:
152        clocks:
153          minItems: 5
154
155        clock-names:
156          items:
157            - const: bus_clk
158            - const: phyclk_mipidphy0_bitclkdiv8
159            - const: phyclk_mipidphy0_rxclkesc0
160            - const: sclk_rgb_vclk_to_dsim0
161            - const: sclk_mipi
162
163        ports:
164          required:
165            - port@0
166
167      required:
168        - ports
169        - vddcore-supply
170        - vddio-supply
171
172  - if:
173      properties:
174        compatible:
175          contains:
176            const: samsung,exynos5410-mipi-dsi
177
178    then:
179      properties:
180        clocks:
181          minItems: 2
182
183        clock-names:
184          items:
185            - const: bus_clk
186            - const: pll_clk
187
188      required:
189        - vddcore-supply
190        - vddio-supply
191
192  - if:
193      properties:
194        compatible:
195          contains:
196            const: samsung,exynos4210-mipi-dsi
197
198    then:
199      properties:
200        clocks:
201          minItems: 2
202
203        clock-names:
204          items:
205            - const: bus_clk
206            - const: sclk_mipi
207
208      required:
209        - vddcore-supply
210        - vddio-supply
211
212  - if:
213      properties:
214        compatible:
215          contains:
216            const: samsung,exynos3250-mipi-dsi
217
218    then:
219      properties:
220        clocks:
221          minItems: 2
222
223        clock-names:
224          items:
225            - const: bus_clk
226            - const: pll_clk
227
228      required:
229        - vddcore-supply
230        - vddio-supply
231        - samsung,phy-type
232
233additionalProperties:
234  type: object
235
236examples:
237  - |
238    #include <dt-bindings/clock/exynos5433.h>
239    #include <dt-bindings/gpio/gpio.h>
240    #include <dt-bindings/interrupt-controller/arm-gic.h>
241
242    dsi@13900000 {
243       compatible = "samsung,exynos5433-mipi-dsi";
244       reg = <0x13900000 0xC0>;
245       interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
246       phys = <&mipi_phy 1>;
247       phy-names = "dsim";
248       clocks = <&cmu_disp CLK_PCLK_DSIM0>,
249                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
250                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
251                <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
252                <&cmu_disp CLK_SCLK_DSIM0>;
253       clock-names = "bus_clk",
254                     "phyclk_mipidphy0_bitclkdiv8",
255                     "phyclk_mipidphy0_rxclkesc0",
256                     "sclk_rgb_vclk_to_dsim0",
257                     "sclk_mipi";
258       power-domains = <&pd_disp>;
259       vddcore-supply = <&ldo6_reg>;
260       vddio-supply = <&ldo7_reg>;
261       samsung,burst-clock-frequency = <512000000>;
262       samsung,esc-clock-frequency = <16000000>;
263       samsung,pll-clock-frequency = <24000000>;
264       pinctrl-names = "default";
265       pinctrl-0 = <&te_irq>;
266
267       ports {
268          #address-cells = <1>;
269          #size-cells = <0>;
270
271          port@0 {
272             reg = <0>;
273
274             dsi_to_mic: endpoint {
275                remote-endpoint = <&mic_to_dsi>;
276             };
277          };
278       };
279    };
280