1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car LVDS Encoder
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11
12description: |
13  These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14  Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
15
16properties:
17  compatible:
18    enum:
19      - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20      - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21      - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
22      - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
23      - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
24      - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
25      - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
26      - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
27      - renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
28      - renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
29      - renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
30      - renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
31      - renesas,r8a77961-lvds # for R-Car M3-W+ compatible LVDS encoders
32      - renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
33      - renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
34      - renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
35      - renesas,r8a77990-lvds # for R-Car E3 compatible LVDS encoders
36      - renesas,r8a77995-lvds # for R-Car D3 compatible LVDS encoders
37
38  reg:
39    maxItems: 1
40
41  clocks:
42    minItems: 1
43    maxItems: 4
44
45  clock-names:
46    minItems: 1
47    maxItems: 4
48
49  resets:
50    maxItems: 1
51
52  ports:
53    $ref: /schemas/graph.yaml#/properties/ports
54
55    properties:
56      port@0:
57        $ref: /schemas/graph.yaml#/properties/port
58        description: Parallel RGB input port
59
60      port@1:
61        $ref: /schemas/graph.yaml#/properties/port
62        description: LVDS output port
63
64    required:
65      - port@0
66      - port@1
67
68  power-domains:
69    maxItems: 1
70
71  renesas,companion:
72    $ref: /schemas/types.yaml#/definitions/phandle
73    description:
74      phandle to the companion LVDS encoder. This property is mandatory
75      for the first LVDS encoder on R-Car D3 and E3, and RZ/G2E SoCs, and shall
76      point to the second encoder to be used as a companion in dual-link mode.
77      It shall not be set for any other LVDS encoder.
78
79required:
80  - compatible
81  - reg
82  - clocks
83  - power-domains
84  - resets
85  - ports
86
87if:
88  properties:
89    compatible:
90      enum:
91        - renesas,r8a774c0-lvds
92        - renesas,r8a77990-lvds
93        - renesas,r8a77995-lvds
94then:
95  properties:
96    clocks:
97      minItems: 1
98      maxItems: 4
99      items:
100        - description: Functional clock
101        - description: EXTAL input clock
102        - description: DU_DOTCLKIN0 input clock
103        - description: DU_DOTCLKIN1 input clock
104
105    clock-names:
106      minItems: 1
107      maxItems: 4
108      items:
109        - const: fck
110        # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
111        # These clocks are optional.
112        - enum:
113            - extal
114            - dclkin.0
115            - dclkin.1
116        - enum:
117            - extal
118            - dclkin.0
119            - dclkin.1
120        - enum:
121            - extal
122            - dclkin.0
123            - dclkin.1
124
125  required:
126    - clock-names
127
128else:
129  properties:
130    clocks:
131      maxItems: 1
132      items:
133        - description: Functional clock
134
135    clock-names:
136      maxItems: 1
137      items:
138        - const: fck
139
140    renesas,companion: false
141
142additionalProperties: false
143
144examples:
145  - |
146    #include <dt-bindings/clock/renesas-cpg-mssr.h>
147    #include <dt-bindings/power/r8a7795-sysc.h>
148
149    lvds@feb90000 {
150        compatible = "renesas,r8a7795-lvds";
151        reg = <0xfeb90000 0x14>;
152        clocks = <&cpg CPG_MOD 727>;
153        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
154        resets = <&cpg 727>;
155
156        ports {
157            #address-cells = <1>;
158            #size-cells = <0>;
159
160            port@0 {
161                reg = <0>;
162                lvds_in: endpoint {
163                    remote-endpoint = <&du_out_lvds0>;
164                };
165            };
166            port@1 {
167                reg = <1>;
168                lvds_out: endpoint {
169                    remote-endpoint = <&panel_in>;
170                };
171            };
172        };
173    };
174
175  - |
176    #include <dt-bindings/clock/renesas-cpg-mssr.h>
177    #include <dt-bindings/power/r8a77990-sysc.h>
178
179    lvds0: lvds@feb90000 {
180        compatible = "renesas,r8a77990-lvds";
181        reg = <0xfeb90000 0x20>;
182        clocks = <&cpg CPG_MOD 727>,
183                 <&x13_clk>,
184                 <&extal_clk>;
185        clock-names = "fck", "dclkin.0", "extal";
186        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
187        resets = <&cpg 727>;
188
189        renesas,companion = <&lvds1>;
190
191        ports {
192            #address-cells = <1>;
193            #size-cells = <0>;
194
195            port@0 {
196                reg = <0>;
197                lvds0_in: endpoint {
198                    remote-endpoint = <&du_out_lvds0>;
199                };
200            };
201            port@1 {
202                reg = <1>;
203                lvds0_out: endpoint {
204                    remote-endpoint = <&panel_in1>;
205                };
206            };
207        };
208    };
209
210    lvds1: lvds@feb90100 {
211        compatible = "renesas,r8a77990-lvds";
212        reg = <0xfeb90100 0x20>;
213        clocks = <&cpg CPG_MOD 727>,
214                 <&x13_clk>,
215                 <&extal_clk>;
216        clock-names = "fck", "dclkin.0", "extal";
217        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
218        resets = <&cpg 726>;
219
220        ports {
221            #address-cells = <1>;
222            #size-cells = <0>;
223
224            port@0 {
225                reg = <0>;
226                lvds1_in: endpoint {
227                    remote-endpoint = <&du_out_lvds1>;
228                };
229            };
230            port@1 {
231                reg = <1>;
232                lvds1_out: endpoint {
233                    remote-endpoint = <&panel_in2>;
234                };
235            };
236        };
237    };
238
239...
240