1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car LVDS Encoder
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11
12description: |
13  These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14  Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
15
16properties:
17  compatible:
18    enum:
19      - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20      - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21      - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
22      - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
23      - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
24      - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
25      - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
26      - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
27      - renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
28      - renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
29      - renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
30      - renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
31      - renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
32      - renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
33      - renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
34      - renesas,r8a77990-lvds # for R-Car E3 compatible LVDS encoders
35      - renesas,r8a77995-lvds # for R-Car D3 compatible LVDS encoders
36
37  reg:
38    maxItems: 1
39
40  clocks:
41    minItems: 1
42    maxItems: 4
43
44  clock-names:
45    minItems: 1
46    maxItems: 4
47
48  resets:
49    maxItems: 1
50
51  ports:
52    $ref: /schemas/graph.yaml#/properties/ports
53
54    properties:
55      port@0:
56        $ref: /schemas/graph.yaml#/properties/port
57        description: Parallel RGB input port
58
59      port@1:
60        $ref: /schemas/graph.yaml#/properties/port
61        description: LVDS output port
62
63    required:
64      - port@0
65      - port@1
66
67  power-domains:
68    maxItems: 1
69
70  renesas,companion:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    description:
73      phandle to the companion LVDS encoder. This property is mandatory
74      for the first LVDS encoder on R-Car D3 and E3, and RZ/G2E SoCs, and shall
75      point to the second encoder to be used as a companion in dual-link mode.
76      It shall not be set for any other LVDS encoder.
77
78required:
79  - compatible
80  - reg
81  - clocks
82  - power-domains
83  - resets
84  - ports
85
86if:
87  properties:
88    compatible:
89      enum:
90        - renesas,r8a774c0-lvds
91        - renesas,r8a77990-lvds
92        - renesas,r8a77995-lvds
93then:
94  properties:
95    clocks:
96      minItems: 1
97      maxItems: 4
98      items:
99        - description: Functional clock
100        - description: EXTAL input clock
101        - description: DU_DOTCLKIN0 input clock
102        - description: DU_DOTCLKIN1 input clock
103
104    clock-names:
105      minItems: 1
106      maxItems: 4
107      items:
108        - const: fck
109        # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
110        # These clocks are optional.
111        - enum:
112            - extal
113            - dclkin.0
114            - dclkin.1
115        - enum:
116            - extal
117            - dclkin.0
118            - dclkin.1
119        - enum:
120            - extal
121            - dclkin.0
122            - dclkin.1
123
124  required:
125    - clock-names
126
127else:
128  properties:
129    clocks:
130      maxItems: 1
131      items:
132        - description: Functional clock
133
134    clock-names:
135      maxItems: 1
136      items:
137        - const: fck
138
139    renesas,companion: false
140
141additionalProperties: false
142
143examples:
144  - |
145    #include <dt-bindings/clock/renesas-cpg-mssr.h>
146    #include <dt-bindings/power/r8a7795-sysc.h>
147
148    lvds@feb90000 {
149        compatible = "renesas,r8a7795-lvds";
150        reg = <0xfeb90000 0x14>;
151        clocks = <&cpg CPG_MOD 727>;
152        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
153        resets = <&cpg 727>;
154
155        ports {
156            #address-cells = <1>;
157            #size-cells = <0>;
158
159            port@0 {
160                reg = <0>;
161                lvds_in: endpoint {
162                    remote-endpoint = <&du_out_lvds0>;
163                };
164            };
165            port@1 {
166                reg = <1>;
167                lvds_out: endpoint {
168                    remote-endpoint = <&panel_in>;
169                };
170            };
171        };
172    };
173
174  - |
175    #include <dt-bindings/clock/renesas-cpg-mssr.h>
176    #include <dt-bindings/power/r8a77990-sysc.h>
177
178    lvds0: lvds@feb90000 {
179        compatible = "renesas,r8a77990-lvds";
180        reg = <0xfeb90000 0x20>;
181        clocks = <&cpg CPG_MOD 727>,
182                 <&x13_clk>,
183                 <&extal_clk>;
184        clock-names = "fck", "dclkin.0", "extal";
185        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
186        resets = <&cpg 727>;
187
188        renesas,companion = <&lvds1>;
189
190        ports {
191            #address-cells = <1>;
192            #size-cells = <0>;
193
194            port@0 {
195                reg = <0>;
196                lvds0_in: endpoint {
197                    remote-endpoint = <&du_out_lvds0>;
198                };
199            };
200            port@1 {
201                reg = <1>;
202                lvds0_out: endpoint {
203                    remote-endpoint = <&panel_in1>;
204                };
205            };
206        };
207    };
208
209    lvds1: lvds@feb90100 {
210        compatible = "renesas,r8a77990-lvds";
211        reg = <0xfeb90100 0x20>;
212        clocks = <&cpg CPG_MOD 727>,
213                 <&x13_clk>,
214                 <&extal_clk>;
215        clock-names = "fck", "dclkin.0", "extal";
216        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
217        resets = <&cpg 726>;
218
219        ports {
220            #address-cells = <1>;
221            #size-cells = <0>;
222
223            port@0 {
224                reg = <0>;
225                lvds1_in: endpoint {
226                    remote-endpoint = <&du_out_lvds1>;
227                };
228            };
229            port@1 {
230                reg = <1>;
231                lvds1_out: endpoint {
232                    remote-endpoint = <&panel_in2>;
233                };
234            };
235        };
236    };
237
238...
239