1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car DWC HDMI TX Encoder 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 12description: | 13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP 14 with a companion PHY IP. 15 16allOf: 17 - $ref: synopsys,dw-hdmi.yaml# 18 19properties: 20 compatible: 21 items: 22 - enum: 23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX 24 - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX 25 - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX 26 - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX 27 - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX 28 - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX 29 - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX 30 - const: renesas,rcar-gen3-hdmi 31 32 reg-io-width: 33 const: 1 34 35 clocks: 36 maxItems: 2 37 38 clock-names: 39 maxItems: 2 40 41 resets: 42 maxItems: 1 43 44 ports: 45 $ref: /schemas/graph.yaml#/properties/ports 46 47 properties: 48 port@0: 49 $ref: /schemas/graph.yaml#/properties/port 50 description: Parallel RGB input port 51 52 port@1: 53 $ref: /schemas/graph.yaml#/properties/port 54 description: HDMI output port 55 56 port@2: 57 $ref: /schemas/graph.yaml#/properties/port 58 description: Sound input port 59 60 required: 61 - port@0 62 - port@1 63 - port@2 64 65 power-domains: 66 maxItems: 1 67 68required: 69 - compatible 70 - reg 71 - clocks 72 - clock-names 73 - resets 74 - interrupts 75 - ports 76 77unevaluatedProperties: false 78 79examples: 80 - | 81 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 82 #include <dt-bindings/interrupt-controller/irq.h> 83 #include <dt-bindings/power/r8a7795-sysc.h> 84 85 hdmi@fead0000 { 86 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 87 reg = <0xfead0000 0x10000>; 88 interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; 90 clock-names = "iahb", "isfr"; 91 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 92 resets = <&cpg 729>; 93 94 ports { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 port@0 { 98 reg = <0>; 99 dw_hdmi0_in: endpoint { 100 remote-endpoint = <&du_out_hdmi0>; 101 }; 102 }; 103 port@1 { 104 reg = <1>; 105 rcar_dw_hdmi0_out: endpoint { 106 remote-endpoint = <&hdmi0_con>; 107 }; 108 }; 109 port@2 { 110 reg = <2>; 111 rcar_dw_hdmi0_sound_in: endpoint { 112 remote-endpoint = <&hdmi_sound_out>; 113 }; 114 }; 115 }; 116 }; 117 118 hdmi0-out { 119 compatible = "hdmi-connector"; 120 label = "HDMI0 OUT"; 121 type = "a"; 122 123 port { 124 hdmi0_con: endpoint { 125 remote-endpoint = <&rcar_dw_hdmi0_out>; 126 }; 127 }; 128 }; 129 130... 131