16885e66bSGuido Günther# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 26885e66bSGuido Günther%YAML 1.2 36885e66bSGuido Günther--- 46885e66bSGuido Günther$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml# 56885e66bSGuido Günther$schema: http://devicetree.org/meta-schemas/core.yaml# 66885e66bSGuido Günther 76885e66bSGuido Günthertitle: Northwest Logic MIPI-DSI controller on i.MX SoCs 86885e66bSGuido Günther 96885e66bSGuido Günthermaintainers: 106885e66bSGuido Günther - Guido Gúnther <agx@sigxcpu.org> 116885e66bSGuido Günther - Robert Chiras <robert.chiras@nxp.com> 126885e66bSGuido Günther 136885e66bSGuido Güntherdescription: | 146885e66bSGuido Günther NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for 156885e66bSGuido Günther the SOCs NWL MIPI-DSI host controller. 166885e66bSGuido Günther 176885e66bSGuido Güntherproperties: 186885e66bSGuido Günther compatible: 196885e66bSGuido Günther const: fsl,imx8mq-nwl-dsi 206885e66bSGuido Günther 216885e66bSGuido Günther reg: 226885e66bSGuido Günther maxItems: 1 236885e66bSGuido Günther 246885e66bSGuido Günther interrupts: 256885e66bSGuido Günther maxItems: 1 266885e66bSGuido Günther 276885e66bSGuido Günther '#address-cells': 286885e66bSGuido Günther const: 1 296885e66bSGuido Günther 306885e66bSGuido Günther '#size-cells': 316885e66bSGuido Günther const: 0 326885e66bSGuido Günther 336885e66bSGuido Günther clocks: 346885e66bSGuido Günther items: 356885e66bSGuido Günther - description: DSI core clock 366885e66bSGuido Günther - description: RX_ESC clock (used in escape mode) 376885e66bSGuido Günther - description: TX_ESC clock (used in escape mode) 386885e66bSGuido Günther - description: PHY_REF clock 396885e66bSGuido Günther - description: LCDIF clock 406885e66bSGuido Günther 416885e66bSGuido Günther clock-names: 426885e66bSGuido Günther items: 436885e66bSGuido Günther - const: core 446885e66bSGuido Günther - const: rx_esc 456885e66bSGuido Günther - const: tx_esc 466885e66bSGuido Günther - const: phy_ref 476885e66bSGuido Günther - const: lcdif 486885e66bSGuido Günther 496885e66bSGuido Günther mux-controls: 506885e66bSGuido Günther description: 516885e66bSGuido Günther mux controller node to use for operating the input mux 526885e66bSGuido Günther 536885e66bSGuido Günther phys: 546885e66bSGuido Günther maxItems: 1 556885e66bSGuido Günther description: 566885e66bSGuido Günther A phandle to the phy module representing the DPHY 576885e66bSGuido Günther 586885e66bSGuido Günther phy-names: 596885e66bSGuido Günther items: 606885e66bSGuido Günther - const: dphy 616885e66bSGuido Günther 626885e66bSGuido Günther power-domains: 636885e66bSGuido Günther maxItems: 1 646885e66bSGuido Günther 656885e66bSGuido Günther resets: 666885e66bSGuido Günther items: 676885e66bSGuido Günther - description: dsi byte reset line 686885e66bSGuido Günther - description: dsi dpi reset line 696885e66bSGuido Günther - description: dsi esc reset line 706885e66bSGuido Günther - description: dsi pclk reset line 716885e66bSGuido Günther 726885e66bSGuido Günther reset-names: 736885e66bSGuido Günther items: 746885e66bSGuido Günther - const: byte 756885e66bSGuido Günther - const: dpi 766885e66bSGuido Günther - const: esc 776885e66bSGuido Günther - const: pclk 786885e66bSGuido Günther 796885e66bSGuido Günther ports: 806885e66bSGuido Günther type: object 816885e66bSGuido Günther description: 826885e66bSGuido Günther A node containing DSI input & output port nodes with endpoint 836885e66bSGuido Günther definitions as documented in 846885e66bSGuido Günther Documentation/devicetree/bindings/graph.txt. 856885e66bSGuido Günther properties: 866885e66bSGuido Günther port@0: 876885e66bSGuido Günther type: object 886885e66bSGuido Günther description: 896885e66bSGuido Günther Input port node to receive pixel data from the 906885e66bSGuido Günther display controller. Exactly one endpoint must be 916885e66bSGuido Günther specified. 926885e66bSGuido Günther properties: 936885e66bSGuido Günther '#address-cells': 946885e66bSGuido Günther const: 1 956885e66bSGuido Günther 966885e66bSGuido Günther '#size-cells': 976885e66bSGuido Günther const: 0 986885e66bSGuido Günther 996885e66bSGuido Günther endpoint@0: 1006885e66bSGuido Günther description: sub-node describing the input from LCDIF 1016885e66bSGuido Günther type: object 1026885e66bSGuido Günther 1036885e66bSGuido Günther endpoint@1: 1046885e66bSGuido Günther description: sub-node describing the input from DCSS 1056885e66bSGuido Günther type: object 1066885e66bSGuido Günther 1076885e66bSGuido Günther reg: 1086885e66bSGuido Günther const: 0 1096885e66bSGuido Günther 1106885e66bSGuido Günther required: 1116885e66bSGuido Günther - '#address-cells' 1126885e66bSGuido Günther - '#size-cells' 1136885e66bSGuido Günther - reg 1146885e66bSGuido Günther 1156885e66bSGuido Günther oneOf: 1166885e66bSGuido Günther - required: 1176885e66bSGuido Günther - endpoint@0 1186885e66bSGuido Günther - required: 1196885e66bSGuido Günther - endpoint@1 1206885e66bSGuido Günther 1216885e66bSGuido Günther additionalProperties: false 1226885e66bSGuido Günther 1236885e66bSGuido Günther port@1: 1246885e66bSGuido Günther type: object 1256885e66bSGuido Günther description: 1266885e66bSGuido Günther DSI output port node to the panel or the next bridge 1276885e66bSGuido Günther in the chain 1286885e66bSGuido Günther 1296885e66bSGuido Günther '#address-cells': 1306885e66bSGuido Günther const: 1 1316885e66bSGuido Günther 1326885e66bSGuido Günther '#size-cells': 1336885e66bSGuido Günther const: 0 1346885e66bSGuido Günther 1356885e66bSGuido Günther required: 1366885e66bSGuido Günther - '#address-cells' 1376885e66bSGuido Günther - '#size-cells' 1386885e66bSGuido Günther - port@0 1396885e66bSGuido Günther - port@1 1406885e66bSGuido Günther 1416885e66bSGuido Günther additionalProperties: false 1426885e66bSGuido Günther 1436885e66bSGuido GüntherpatternProperties: 1446885e66bSGuido Günther "^panel@[0-9]+$": 1456885e66bSGuido Günther type: object 1466885e66bSGuido Günther 1476885e66bSGuido Güntherrequired: 1486885e66bSGuido Günther - '#address-cells' 1496885e66bSGuido Günther - '#size-cells' 1506885e66bSGuido Günther - clock-names 1516885e66bSGuido Günther - clocks 1526885e66bSGuido Günther - compatible 1536885e66bSGuido Günther - interrupts 1546885e66bSGuido Günther - mux-controls 1556885e66bSGuido Günther - phy-names 1566885e66bSGuido Günther - phys 1576885e66bSGuido Günther - ports 1586885e66bSGuido Günther - reg 1596885e66bSGuido Günther - reset-names 1606885e66bSGuido Günther - resets 1616885e66bSGuido Günther 1626885e66bSGuido GüntheradditionalProperties: false 1636885e66bSGuido Günther 1646885e66bSGuido Güntherexamples: 1656885e66bSGuido Günther - | 1666885e66bSGuido Günther 1676885e66bSGuido Günther #include <dt-bindings/clock/imx8mq-clock.h> 168724884c3SOndrej Jirman #include <dt-bindings/gpio/gpio.h> 1696885e66bSGuido Günther #include <dt-bindings/interrupt-controller/arm-gic.h> 1706885e66bSGuido Günther #include <dt-bindings/reset/imx8mq-reset.h> 1716885e66bSGuido Günther 1726885e66bSGuido Günther mipi_dsi: mipi_dsi@30a00000 { 1736885e66bSGuido Günther #address-cells = <1>; 1746885e66bSGuido Günther #size-cells = <0>; 1756885e66bSGuido Günther compatible = "fsl,imx8mq-nwl-dsi"; 1766885e66bSGuido Günther reg = <0x30A00000 0x300>; 1776885e66bSGuido Günther clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 1786885e66bSGuido Günther <&clk IMX8MQ_CLK_DSI_AHB>, 1796885e66bSGuido Günther <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 1806885e66bSGuido Günther <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1816885e66bSGuido Günther <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 1826885e66bSGuido Günther clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 1836885e66bSGuido Günther interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1846885e66bSGuido Günther mux-controls = <&mux 0>; 1856885e66bSGuido Günther power-domains = <&pgc_mipi>; 1866885e66bSGuido Günther resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 1876885e66bSGuido Günther <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 1886885e66bSGuido Günther <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 1896885e66bSGuido Günther <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 1906885e66bSGuido Günther reset-names = "byte", "dpi", "esc", "pclk"; 1916885e66bSGuido Günther phys = <&dphy>; 1926885e66bSGuido Günther phy-names = "dphy"; 1936885e66bSGuido Günther 1946885e66bSGuido Günther panel@0 { 1956885e66bSGuido Günther compatible = "rocktech,jh057n00900"; 1966885e66bSGuido Günther reg = <0>; 197724884c3SOndrej Jirman vcc-supply = <®_2v8_p>; 198724884c3SOndrej Jirman iovcc-supply = <®_1v8_p>; 199724884c3SOndrej Jirman reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; 200724884c3SOndrej Jirman port { 2016885e66bSGuido Günther panel_in: endpoint { 2026885e66bSGuido Günther remote-endpoint = <&mipi_dsi_out>; 2036885e66bSGuido Günther }; 2046885e66bSGuido Günther }; 2056885e66bSGuido Günther }; 2066885e66bSGuido Günther 2076885e66bSGuido Günther ports { 2086885e66bSGuido Günther #address-cells = <1>; 2096885e66bSGuido Günther #size-cells = <0>; 2106885e66bSGuido Günther 2116885e66bSGuido Günther port@0 { 2126885e66bSGuido Günther #size-cells = <0>; 2136885e66bSGuido Günther #address-cells = <1>; 2146885e66bSGuido Günther reg = <0>; 2156885e66bSGuido Günther mipi_dsi_in: endpoint@0 { 2166885e66bSGuido Günther reg = <0>; 2176885e66bSGuido Günther remote-endpoint = <&lcdif_mipi_dsi>; 2186885e66bSGuido Günther }; 2196885e66bSGuido Günther }; 2206885e66bSGuido Günther port@1 { 2216885e66bSGuido Günther reg = <1>; 2226885e66bSGuido Günther mipi_dsi_out: endpoint { 2236885e66bSGuido Günther remote-endpoint = <&panel_in>; 2246885e66bSGuido Günther }; 2256885e66bSGuido Günther }; 2266885e66bSGuido Günther }; 2276885e66bSGuido Günther }; 228