1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Cadence MHDP8546 bridge
8
9maintainers:
10  - Swapnil Jakhade <sjakhade@cadence.com>
11  - Yuti Amonkar <yamonkar@cadence.com>
12
13properties:
14  compatible:
15    enum:
16      - cdns,mhdp8546
17      - ti,j721e-mhdp8546
18
19  reg:
20    minItems: 1
21    maxItems: 2
22    items:
23      - description:
24          Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
25          The AUX and PMA registers are not part of this range, they are instead
26          included in the associated PHY.
27      - description:
28          Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
29
30  reg-names:
31    minItems: 1
32    maxItems: 2
33    items:
34      - const: mhdptx
35      - const: j721e-intg
36
37  clocks:
38    maxItems: 1
39    description:
40      DP bridge clock, used by the IP to know how to translate a number of
41      clock cycles into a time (which is used to comply with DP standard timings
42      and delays).
43
44  phys:
45    maxItems: 1
46    description:
47      phandle to the DisplayPort PHY.
48
49  phy-names:
50    items:
51      - const: dpphy
52
53  power-domains:
54    maxItems: 1
55
56  interrupts:
57    maxItems: 1
58
59  ports:
60    $ref: /schemas/graph.yaml#/properties/ports
61
62    properties:
63      port@0:
64        $ref: /schemas/graph.yaml#/properties/port
65        description:
66          First input port representing the DP bridge input.
67
68      port@1:
69        $ref: /schemas/graph.yaml#/properties/port
70        description:
71          Second input port representing the DP bridge input.
72
73      port@2:
74        $ref: /schemas/graph.yaml#/properties/port
75        description:
76          Third input port representing the DP bridge input.
77
78      port@3:
79        $ref: /schemas/graph.yaml#/properties/port
80        description:
81          Fourth input port representing the DP bridge input.
82
83      port@4:
84        $ref: /schemas/graph.yaml#/properties/port
85        description:
86          Output port representing the DP bridge output.
87
88    required:
89      - port@0
90      - port@4
91
92allOf:
93  - if:
94      properties:
95        compatible:
96          contains:
97            const: ti,j721e-mhdp8546
98    then:
99      properties:
100        reg:
101          minItems: 2
102        reg-names:
103          minItems: 2
104    else:
105      properties:
106        reg:
107          maxItems: 1
108        reg-names:
109          maxItems: 1
110
111required:
112  - compatible
113  - clocks
114  - reg
115  - reg-names
116  - phys
117  - phy-names
118  - interrupts
119  - ports
120
121additionalProperties: false
122
123examples:
124  - |
125    #include <dt-bindings/interrupt-controller/arm-gic.h>
126    bus {
127        #address-cells = <2>;
128        #size-cells = <2>;
129
130        mhdp: dp-bridge@f0fb000000 {
131            compatible = "cdns,mhdp8546";
132            reg = <0xf0 0xfb000000 0x0 0x1000000>;
133            reg-names = "mhdptx";
134            clocks = <&mhdp_clock>;
135            phys = <&dp_phy>;
136            phy-names = "dpphy";
137            interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
138
139            ports {
140                #address-cells = <1>;
141                #size-cells = <0>;
142
143                port@0 {
144                    reg = <0>;
145                    dp_bridge_input: endpoint {
146                        remote-endpoint = <&xxx_dpi_output>;
147                    };
148                };
149
150                port@4 {
151                    reg = <4>;
152                    dp_bridge_output: endpoint {
153                        remote-endpoint = <&xxx_dp_connector_input>;
154                    };
155                };
156            };
157        };
158    };
159...
160