159b2deaeSRahul T R# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
259b2deaeSRahul T R%YAML 1.2
359b2deaeSRahul T R---
459b2deaeSRahul T R$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml#
559b2deaeSRahul T R$schema: http://devicetree.org/meta-schemas/core.yaml#
659b2deaeSRahul T R
759b2deaeSRahul T Rtitle: Cadence DSI bridge
859b2deaeSRahul T R
959b2deaeSRahul T Rmaintainers:
1059b2deaeSRahul T R  - Boris Brezillon <boris.brezillon@bootlin.com>
1159b2deaeSRahul T R
1259b2deaeSRahul T Rdescription: |
1359b2deaeSRahul T R   CDNS DSI is a bridge device which converts DPI to DSI
1459b2deaeSRahul T R
1559b2deaeSRahul T Rproperties:
1659b2deaeSRahul T R  compatible:
1759b2deaeSRahul T R    enum:
1859b2deaeSRahul T R      - cdns,dsi
19*6f209ca0SRahul T R      - ti,j721e-dsi
2059b2deaeSRahul T R
2159b2deaeSRahul T R  reg:
22*6f209ca0SRahul T R    minItems: 1
23*6f209ca0SRahul T R    items:
24*6f209ca0SRahul T R      - description:
25*6f209ca0SRahul T R          Register block for controller's registers.
26*6f209ca0SRahul T R      - description:
27*6f209ca0SRahul T R          Register block for wrapper settings registers in case of TI J7 SoCs.
2859b2deaeSRahul T R
2959b2deaeSRahul T R  clocks:
3059b2deaeSRahul T R    items:
3159b2deaeSRahul T R      - description: PSM clock, used by the IP
3259b2deaeSRahul T R      - description: sys clock, used by the IP
3359b2deaeSRahul T R
3459b2deaeSRahul T R  clock-names:
3559b2deaeSRahul T R    items:
3659b2deaeSRahul T R      - const: dsi_p_clk
3759b2deaeSRahul T R      - const: dsi_sys_clk
3859b2deaeSRahul T R
3959b2deaeSRahul T R  phys:
4059b2deaeSRahul T R    maxItems: 1
4159b2deaeSRahul T R
4259b2deaeSRahul T R  phy-names:
4359b2deaeSRahul T R    const: dphy
4459b2deaeSRahul T R
4559b2deaeSRahul T R  interrupts:
4659b2deaeSRahul T R    maxItems: 1
4759b2deaeSRahul T R
4859b2deaeSRahul T R  resets:
4959b2deaeSRahul T R    maxItems: 1
5059b2deaeSRahul T R
5159b2deaeSRahul T R  reset-names:
5259b2deaeSRahul T R    const: dsi_p_rst
5359b2deaeSRahul T R
5459b2deaeSRahul T R  ports:
5559b2deaeSRahul T R    $ref: /schemas/graph.yaml#/properties/ports
5659b2deaeSRahul T R
5759b2deaeSRahul T R    properties:
5859b2deaeSRahul T R      port@0:
5959b2deaeSRahul T R        $ref: /schemas/graph.yaml#/properties/port
6059b2deaeSRahul T R        description:
6159b2deaeSRahul T R          Output port representing the DSI output. It can have
6259b2deaeSRahul T R          at most 4 endpoints. The endpoint number is directly encoding
6359b2deaeSRahul T R          the DSI virtual channel used by this device.
6459b2deaeSRahul T R
6559b2deaeSRahul T R      port@1:
6659b2deaeSRahul T R        $ref: /schemas/graph.yaml#/properties/port
6759b2deaeSRahul T R        description:
6859b2deaeSRahul T R          Input port representing the DPI input.
6959b2deaeSRahul T R
7059b2deaeSRahul T R    required:
7159b2deaeSRahul T R      - port@1
7259b2deaeSRahul T R
7359b2deaeSRahul T RallOf:
7459b2deaeSRahul T R  - $ref: ../dsi-controller.yaml#
7559b2deaeSRahul T R
76*6f209ca0SRahul T R  - if:
77*6f209ca0SRahul T R      properties:
78*6f209ca0SRahul T R        compatible:
79*6f209ca0SRahul T R          contains:
80*6f209ca0SRahul T R            const: ti,j721e-dsi
81*6f209ca0SRahul T R    then:
82*6f209ca0SRahul T R      properties:
83*6f209ca0SRahul T R        reg:
84*6f209ca0SRahul T R          minItems: 2
85*6f209ca0SRahul T R          maxItems: 2
86*6f209ca0SRahul T R        power-domains:
87*6f209ca0SRahul T R          maxItems: 1
88*6f209ca0SRahul T R    else:
89*6f209ca0SRahul T R      properties:
90*6f209ca0SRahul T R        reg:
91*6f209ca0SRahul T R          maxItems: 1
92*6f209ca0SRahul T R
9359b2deaeSRahul T Rrequired:
9459b2deaeSRahul T R  - compatible
9559b2deaeSRahul T R  - reg
9659b2deaeSRahul T R  - interrupts
9759b2deaeSRahul T R  - clocks
9859b2deaeSRahul T R  - clock-names
9959b2deaeSRahul T R  - phys
10059b2deaeSRahul T R  - phy-names
10159b2deaeSRahul T R  - ports
10259b2deaeSRahul T R
10359b2deaeSRahul T RunevaluatedProperties: false
10459b2deaeSRahul T R
10559b2deaeSRahul T Rexamples:
10659b2deaeSRahul T R  - |
10759b2deaeSRahul T R    bus {
10859b2deaeSRahul T R        #address-cells = <2>;
10959b2deaeSRahul T R        #size-cells = <2>;
11059b2deaeSRahul T R
11159b2deaeSRahul T R        dsi@fd0c0000 {
11259b2deaeSRahul T R            compatible = "cdns,dsi";
11359b2deaeSRahul T R            reg = <0x0 0xfd0c0000 0x0 0x1000>;
11459b2deaeSRahul T R            clocks = <&pclk>, <&sysclk>;
11559b2deaeSRahul T R            clock-names = "dsi_p_clk", "dsi_sys_clk";
11659b2deaeSRahul T R            interrupts = <1>;
11759b2deaeSRahul T R            phys = <&dphy0>;
11859b2deaeSRahul T R            phy-names = "dphy";
11959b2deaeSRahul T R
12059b2deaeSRahul T R            #address-cells = <1>;
12159b2deaeSRahul T R            #size-cells = <0>;
12259b2deaeSRahul T R
12359b2deaeSRahul T R            ports {
12459b2deaeSRahul T R                #address-cells = <1>;
12559b2deaeSRahul T R                #size-cells = <0>;
12659b2deaeSRahul T R
12759b2deaeSRahul T R                port@1 {
12859b2deaeSRahul T R                    reg = <1>;
12959b2deaeSRahul T R                    endpoint {
13059b2deaeSRahul T R                        remote-endpoint = <&xxx_dpi_output>;
13159b2deaeSRahul T R                    };
13259b2deaeSRahul T R                };
13359b2deaeSRahul T R            };
13459b2deaeSRahul T R
13559b2deaeSRahul T R            panel@0 {
13659b2deaeSRahul T R                compatible = "panasonic,vvx10f034n00";
13759b2deaeSRahul T R                reg = <0>;
13859b2deaeSRahul T R                power-supply = <&vcc_lcd_reg>;
13959b2deaeSRahul T R            };
14059b2deaeSRahul T R        };
14159b2deaeSRahul T R    };
14259b2deaeSRahul T R
14359b2deaeSRahul T R  - |
14459b2deaeSRahul T R    bus {
14559b2deaeSRahul T R        #address-cells = <2>;
14659b2deaeSRahul T R        #size-cells = <2>;
14759b2deaeSRahul T R
14859b2deaeSRahul T R        dsi@fd0c0000 {
14959b2deaeSRahul T R            compatible = "cdns,dsi";
15059b2deaeSRahul T R            reg = <0x0 0xfd0c0000 0x0 0x1000>;
15159b2deaeSRahul T R            clocks = <&pclk>, <&sysclk>;
15259b2deaeSRahul T R            clock-names = "dsi_p_clk", "dsi_sys_clk";
15359b2deaeSRahul T R            interrupts = <1>;
15459b2deaeSRahul T R            phys = <&dphy1>;
15559b2deaeSRahul T R            phy-names = "dphy";
15659b2deaeSRahul T R
15759b2deaeSRahul T R            ports {
15859b2deaeSRahul T R                #address-cells = <1>;
15959b2deaeSRahul T R                #size-cells = <0>;
16059b2deaeSRahul T R
16159b2deaeSRahul T R                port@0 {
16259b2deaeSRahul T R                    reg = <0>;
16359b2deaeSRahul T R                    #address-cells = <1>;
16459b2deaeSRahul T R                    #size-cells = <0>;
16559b2deaeSRahul T R
16659b2deaeSRahul T R                    endpoint@0 {
16759b2deaeSRahul T R                        reg = <0>;
16859b2deaeSRahul T R                        remote-endpoint = <&dsi_panel_input>;
16959b2deaeSRahul T R                    };
17059b2deaeSRahul T R                };
17159b2deaeSRahul T R
17259b2deaeSRahul T R                port@1 {
17359b2deaeSRahul T R                    reg = <1>;
17459b2deaeSRahul T R                    endpoint {
17559b2deaeSRahul T R                        remote-endpoint = <&xxx_dpi_output>;
17659b2deaeSRahul T R                    };
17759b2deaeSRahul T R                };
17859b2deaeSRahul T R            };
17959b2deaeSRahul T R        };
18059b2deaeSRahul T R    };
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