185649cc8SYuti Amonkar# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
285649cc8SYuti Amonkar%YAML 1.2
385649cc8SYuti Amonkar---
485649cc8SYuti Amonkar$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
585649cc8SYuti Amonkar$schema: "http://devicetree.org/meta-schemas/core.yaml#"
685649cc8SYuti Amonkar
785649cc8SYuti Amonkartitle: Cadence MHDP8546 bridge
885649cc8SYuti Amonkar
985649cc8SYuti Amonkarmaintainers:
1085649cc8SYuti Amonkar  - Swapnil Jakhade <sjakhade@cadence.com>
1185649cc8SYuti Amonkar  - Yuti Amonkar <yamonkar@cadence.com>
1285649cc8SYuti Amonkar
1385649cc8SYuti Amonkarproperties:
1485649cc8SYuti Amonkar  compatible:
1585649cc8SYuti Amonkar    enum:
1685649cc8SYuti Amonkar      - cdns,mhdp8546
1785649cc8SYuti Amonkar      - ti,j721e-mhdp8546
1885649cc8SYuti Amonkar
1985649cc8SYuti Amonkar  reg:
2085649cc8SYuti Amonkar    minItems: 1
2185649cc8SYuti Amonkar    maxItems: 2
2285649cc8SYuti Amonkar    items:
2385649cc8SYuti Amonkar      - description:
2485649cc8SYuti Amonkar          Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
2585649cc8SYuti Amonkar          The AUX and PMA registers are not part of this range, they are instead
2685649cc8SYuti Amonkar          included in the associated PHY.
2785649cc8SYuti Amonkar      - description:
2885649cc8SYuti Amonkar          Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
2985649cc8SYuti Amonkar
3085649cc8SYuti Amonkar  reg-names:
3185649cc8SYuti Amonkar    minItems: 1
3285649cc8SYuti Amonkar    maxItems: 2
3385649cc8SYuti Amonkar    items:
3485649cc8SYuti Amonkar      - const: mhdptx
3585649cc8SYuti Amonkar      - const: j721e-intg
3685649cc8SYuti Amonkar
3785649cc8SYuti Amonkar  clocks:
3885649cc8SYuti Amonkar    maxItems: 1
3985649cc8SYuti Amonkar    description:
4085649cc8SYuti Amonkar      DP bridge clock, used by the IP to know how to translate a number of
4185649cc8SYuti Amonkar      clock cycles into a time (which is used to comply with DP standard timings
4285649cc8SYuti Amonkar      and delays).
4385649cc8SYuti Amonkar
4485649cc8SYuti Amonkar  phys:
4585649cc8SYuti Amonkar    maxItems: 1
4685649cc8SYuti Amonkar    description:
4785649cc8SYuti Amonkar      phandle to the DisplayPort PHY.
4885649cc8SYuti Amonkar
4985649cc8SYuti Amonkar  phy-names:
5085649cc8SYuti Amonkar    items:
5185649cc8SYuti Amonkar      - const: dpphy
5285649cc8SYuti Amonkar
5385649cc8SYuti Amonkar  power-domains:
5485649cc8SYuti Amonkar    maxItems: 1
5585649cc8SYuti Amonkar
5685649cc8SYuti Amonkar  interrupts:
5785649cc8SYuti Amonkar    maxItems: 1
5885649cc8SYuti Amonkar
5985649cc8SYuti Amonkar  ports:
6085649cc8SYuti Amonkar    type: object
6185649cc8SYuti Amonkar    description:
6285649cc8SYuti Amonkar      Ports as described in Documentation/devicetree/bindings/graph.txt.
6385649cc8SYuti Amonkar
6485649cc8SYuti Amonkar    properties:
6585649cc8SYuti Amonkar      '#address-cells':
6685649cc8SYuti Amonkar        const: 1
6785649cc8SYuti Amonkar
6885649cc8SYuti Amonkar      '#size-cells':
6985649cc8SYuti Amonkar        const: 0
7085649cc8SYuti Amonkar
7185649cc8SYuti Amonkar      port@0:
7285649cc8SYuti Amonkar        type: object
7385649cc8SYuti Amonkar        description:
7485649cc8SYuti Amonkar          First input port representing the DP bridge input.
7585649cc8SYuti Amonkar
7685649cc8SYuti Amonkar      port@1:
7785649cc8SYuti Amonkar        type: object
7885649cc8SYuti Amonkar        description:
7985649cc8SYuti Amonkar          Second input port representing the DP bridge input.
8085649cc8SYuti Amonkar
8185649cc8SYuti Amonkar      port@2:
8285649cc8SYuti Amonkar        type: object
8385649cc8SYuti Amonkar        description:
8485649cc8SYuti Amonkar          Third input port representing the DP bridge input.
8585649cc8SYuti Amonkar
8685649cc8SYuti Amonkar      port@3:
8785649cc8SYuti Amonkar        type: object
8885649cc8SYuti Amonkar        description:
8985649cc8SYuti Amonkar          Fourth input port representing the DP bridge input.
9085649cc8SYuti Amonkar
9185649cc8SYuti Amonkar      port@4:
9285649cc8SYuti Amonkar        type: object
9385649cc8SYuti Amonkar        description:
9485649cc8SYuti Amonkar          Output port representing the DP bridge output.
9585649cc8SYuti Amonkar
9685649cc8SYuti Amonkar    required:
9785649cc8SYuti Amonkar      - port@0
9885649cc8SYuti Amonkar      - port@4
9985649cc8SYuti Amonkar      - '#address-cells'
10085649cc8SYuti Amonkar      - '#size-cells'
10185649cc8SYuti Amonkar
10285649cc8SYuti AmonkarallOf:
10385649cc8SYuti Amonkar  - if:
10485649cc8SYuti Amonkar      properties:
10585649cc8SYuti Amonkar        compatible:
10685649cc8SYuti Amonkar          contains:
10785649cc8SYuti Amonkar            const: ti,j721e-mhdp8546
10885649cc8SYuti Amonkar    then:
10985649cc8SYuti Amonkar      properties:
11085649cc8SYuti Amonkar        reg:
11185649cc8SYuti Amonkar          minItems: 2
11285649cc8SYuti Amonkar        reg-names:
11385649cc8SYuti Amonkar          minItems: 2
11485649cc8SYuti Amonkar    else:
11585649cc8SYuti Amonkar      properties:
11685649cc8SYuti Amonkar        reg:
11785649cc8SYuti Amonkar          maxItems: 1
11885649cc8SYuti Amonkar        reg-names:
11985649cc8SYuti Amonkar          maxItems: 1
12085649cc8SYuti Amonkar
12185649cc8SYuti Amonkarrequired:
12285649cc8SYuti Amonkar  - compatible
12385649cc8SYuti Amonkar  - clocks
12485649cc8SYuti Amonkar  - reg
12585649cc8SYuti Amonkar  - reg-names
12685649cc8SYuti Amonkar  - phys
12785649cc8SYuti Amonkar  - phy-names
12885649cc8SYuti Amonkar  - interrupts
12985649cc8SYuti Amonkar  - ports
13085649cc8SYuti Amonkar
13185649cc8SYuti AmonkaradditionalProperties: false
13285649cc8SYuti Amonkar
13385649cc8SYuti Amonkarexamples:
13485649cc8SYuti Amonkar  - |
13585649cc8SYuti Amonkar    #include <dt-bindings/interrupt-controller/arm-gic.h>
13685649cc8SYuti Amonkar    bus {
13785649cc8SYuti Amonkar        #address-cells = <2>;
13885649cc8SYuti Amonkar        #size-cells = <2>;
13985649cc8SYuti Amonkar
14085649cc8SYuti Amonkar        mhdp: dp-bridge@f0fb000000 {
14185649cc8SYuti Amonkar            compatible = "cdns,mhdp8546";
14285649cc8SYuti Amonkar            reg = <0xf0 0xfb000000 0x0 0x1000000>;
14385649cc8SYuti Amonkar            reg-names = "mhdptx";
14485649cc8SYuti Amonkar            clocks = <&mhdp_clock>;
14585649cc8SYuti Amonkar            phys = <&dp_phy>;
14685649cc8SYuti Amonkar            phy-names = "dpphy";
14785649cc8SYuti Amonkar            interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
14885649cc8SYuti Amonkar
14985649cc8SYuti Amonkar            ports {
15085649cc8SYuti Amonkar                #address-cells = <1>;
15185649cc8SYuti Amonkar                #size-cells = <0>;
15285649cc8SYuti Amonkar
15385649cc8SYuti Amonkar                port@0 {
15485649cc8SYuti Amonkar                    reg = <0>;
15585649cc8SYuti Amonkar                    dp_bridge_input: endpoint {
15685649cc8SYuti Amonkar                        remote-endpoint = <&xxx_dpi_output>;
15785649cc8SYuti Amonkar                    };
15885649cc8SYuti Amonkar                };
15985649cc8SYuti Amonkar
16085649cc8SYuti Amonkar                port@4 {
16185649cc8SYuti Amonkar                    reg = <4>;
16285649cc8SYuti Amonkar                    dp_bridge_output: endpoint {
16385649cc8SYuti Amonkar                        remote-endpoint = <&xxx_dp_connector_input>;
16485649cc8SYuti Amonkar                    };
16585649cc8SYuti Amonkar                };
16685649cc8SYuti Amonkar            };
16785649cc8SYuti Amonkar        };
16885649cc8SYuti Amonkar    };
16985649cc8SYuti Amonkar...
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