185649cc8SYuti Amonkar# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 285649cc8SYuti Amonkar%YAML 1.2 385649cc8SYuti Amonkar--- 485649cc8SYuti Amonkar$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#" 585649cc8SYuti Amonkar$schema: "http://devicetree.org/meta-schemas/core.yaml#" 685649cc8SYuti Amonkar 785649cc8SYuti Amonkartitle: Cadence MHDP8546 bridge 885649cc8SYuti Amonkar 985649cc8SYuti Amonkarmaintainers: 1085649cc8SYuti Amonkar - Swapnil Jakhade <sjakhade@cadence.com> 1185649cc8SYuti Amonkar - Yuti Amonkar <yamonkar@cadence.com> 1285649cc8SYuti Amonkar 1385649cc8SYuti Amonkarproperties: 1485649cc8SYuti Amonkar compatible: 1585649cc8SYuti Amonkar enum: 1685649cc8SYuti Amonkar - cdns,mhdp8546 1785649cc8SYuti Amonkar - ti,j721e-mhdp8546 1885649cc8SYuti Amonkar 1985649cc8SYuti Amonkar reg: 2085649cc8SYuti Amonkar minItems: 1 21*7169d082SParshuram Thombare maxItems: 3 2285649cc8SYuti Amonkar items: 2385649cc8SYuti Amonkar - description: 2485649cc8SYuti Amonkar Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). 2585649cc8SYuti Amonkar The AUX and PMA registers are not part of this range, they are instead 2685649cc8SYuti Amonkar included in the associated PHY. 2785649cc8SYuti Amonkar - description: 2885649cc8SYuti Amonkar Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. 29*7169d082SParshuram Thombare - description: 30*7169d082SParshuram Thombare Register block of mhdptx sapb registers. 3185649cc8SYuti Amonkar 3285649cc8SYuti Amonkar reg-names: 3385649cc8SYuti Amonkar minItems: 1 34*7169d082SParshuram Thombare maxItems: 3 3585649cc8SYuti Amonkar items: 3685649cc8SYuti Amonkar - const: mhdptx 3785649cc8SYuti Amonkar - const: j721e-intg 38*7169d082SParshuram Thombare - const: mhdptx-sapb 3985649cc8SYuti Amonkar 4085649cc8SYuti Amonkar clocks: 4185649cc8SYuti Amonkar maxItems: 1 4285649cc8SYuti Amonkar description: 4385649cc8SYuti Amonkar DP bridge clock, used by the IP to know how to translate a number of 4485649cc8SYuti Amonkar clock cycles into a time (which is used to comply with DP standard timings 4585649cc8SYuti Amonkar and delays). 4685649cc8SYuti Amonkar 4785649cc8SYuti Amonkar phys: 4885649cc8SYuti Amonkar maxItems: 1 4985649cc8SYuti Amonkar description: 5085649cc8SYuti Amonkar phandle to the DisplayPort PHY. 5185649cc8SYuti Amonkar 5285649cc8SYuti Amonkar phy-names: 5385649cc8SYuti Amonkar items: 5485649cc8SYuti Amonkar - const: dpphy 5585649cc8SYuti Amonkar 5685649cc8SYuti Amonkar power-domains: 5785649cc8SYuti Amonkar maxItems: 1 5885649cc8SYuti Amonkar 5985649cc8SYuti Amonkar interrupts: 6085649cc8SYuti Amonkar maxItems: 1 6185649cc8SYuti Amonkar 6285649cc8SYuti Amonkar ports: 63b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/ports 6485649cc8SYuti Amonkar 6585649cc8SYuti Amonkar properties: 6685649cc8SYuti Amonkar port@0: 67b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 6885649cc8SYuti Amonkar description: 6985649cc8SYuti Amonkar First input port representing the DP bridge input. 7085649cc8SYuti Amonkar 7185649cc8SYuti Amonkar port@1: 72b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 7385649cc8SYuti Amonkar description: 7485649cc8SYuti Amonkar Second input port representing the DP bridge input. 7585649cc8SYuti Amonkar 7685649cc8SYuti Amonkar port@2: 77b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 7885649cc8SYuti Amonkar description: 7985649cc8SYuti Amonkar Third input port representing the DP bridge input. 8085649cc8SYuti Amonkar 8185649cc8SYuti Amonkar port@3: 82b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 8385649cc8SYuti Amonkar description: 8485649cc8SYuti Amonkar Fourth input port representing the DP bridge input. 8585649cc8SYuti Amonkar 8685649cc8SYuti Amonkar port@4: 87b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 8885649cc8SYuti Amonkar description: 8985649cc8SYuti Amonkar Output port representing the DP bridge output. 9085649cc8SYuti Amonkar 9185649cc8SYuti Amonkar required: 9285649cc8SYuti Amonkar - port@0 9385649cc8SYuti Amonkar - port@4 9485649cc8SYuti Amonkar 9585649cc8SYuti AmonkarallOf: 9685649cc8SYuti Amonkar - if: 9785649cc8SYuti Amonkar properties: 9885649cc8SYuti Amonkar compatible: 9985649cc8SYuti Amonkar contains: 10085649cc8SYuti Amonkar const: ti,j721e-mhdp8546 10185649cc8SYuti Amonkar then: 10285649cc8SYuti Amonkar properties: 10385649cc8SYuti Amonkar reg: 10485649cc8SYuti Amonkar minItems: 2 105*7169d082SParshuram Thombare maxItems: 3 10685649cc8SYuti Amonkar reg-names: 10785649cc8SYuti Amonkar minItems: 2 108*7169d082SParshuram Thombare maxItems: 3 10985649cc8SYuti Amonkar else: 11085649cc8SYuti Amonkar properties: 11185649cc8SYuti Amonkar reg: 112*7169d082SParshuram Thombare minItems: 1 113*7169d082SParshuram Thombare maxItems: 2 11485649cc8SYuti Amonkar reg-names: 115*7169d082SParshuram Thombare minItems: 1 116*7169d082SParshuram Thombare maxItems: 2 11785649cc8SYuti Amonkar 11885649cc8SYuti Amonkarrequired: 11985649cc8SYuti Amonkar - compatible 12085649cc8SYuti Amonkar - clocks 12185649cc8SYuti Amonkar - reg 12285649cc8SYuti Amonkar - reg-names 12385649cc8SYuti Amonkar - phys 12485649cc8SYuti Amonkar - phy-names 12585649cc8SYuti Amonkar - interrupts 12685649cc8SYuti Amonkar - ports 12785649cc8SYuti Amonkar 12885649cc8SYuti AmonkaradditionalProperties: false 12985649cc8SYuti Amonkar 13085649cc8SYuti Amonkarexamples: 13185649cc8SYuti Amonkar - | 13285649cc8SYuti Amonkar #include <dt-bindings/interrupt-controller/arm-gic.h> 13385649cc8SYuti Amonkar bus { 13485649cc8SYuti Amonkar #address-cells = <2>; 13585649cc8SYuti Amonkar #size-cells = <2>; 13685649cc8SYuti Amonkar 13785649cc8SYuti Amonkar mhdp: dp-bridge@f0fb000000 { 13885649cc8SYuti Amonkar compatible = "cdns,mhdp8546"; 13985649cc8SYuti Amonkar reg = <0xf0 0xfb000000 0x0 0x1000000>; 14085649cc8SYuti Amonkar reg-names = "mhdptx"; 14185649cc8SYuti Amonkar clocks = <&mhdp_clock>; 14285649cc8SYuti Amonkar phys = <&dp_phy>; 14385649cc8SYuti Amonkar phy-names = "dpphy"; 14485649cc8SYuti Amonkar interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 14585649cc8SYuti Amonkar 14685649cc8SYuti Amonkar ports { 14785649cc8SYuti Amonkar #address-cells = <1>; 14885649cc8SYuti Amonkar #size-cells = <0>; 14985649cc8SYuti Amonkar 15085649cc8SYuti Amonkar port@0 { 15185649cc8SYuti Amonkar reg = <0>; 15285649cc8SYuti Amonkar dp_bridge_input: endpoint { 15385649cc8SYuti Amonkar remote-endpoint = <&xxx_dpi_output>; 15485649cc8SYuti Amonkar }; 15585649cc8SYuti Amonkar }; 15685649cc8SYuti Amonkar 15785649cc8SYuti Amonkar port@4 { 15885649cc8SYuti Amonkar reg = <4>; 15985649cc8SYuti Amonkar dp_bridge_output: endpoint { 16085649cc8SYuti Amonkar remote-endpoint = <&xxx_dp_connector_input>; 16185649cc8SYuti Amonkar }; 16285649cc8SYuti Amonkar }; 16385649cc8SYuti Amonkar }; 16485649cc8SYuti Amonkar }; 16585649cc8SYuti Amonkar }; 16685649cc8SYuti Amonkar... 167