1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
8
9description: |
10  The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11  IP with Allwinner\'s own PHY IP. It supports audio and video outputs
12  and CEC.
13
14  These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15  in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
16  the following device-specific properties.
17
18maintainers:
19  - Chen-Yu Tsai <wens@csie.org>
20  - Maxime Ripard <mripard@kernel.org>
21
22properties:
23  "#phy-cells":
24    const: 0
25
26  compatible:
27    oneOf:
28      - const: allwinner,sun8i-a83t-dw-hdmi
29      - const: allwinner,sun50i-h6-dw-hdmi
30
31      - items:
32        - enum:
33          - allwinner,sun8i-h3-dw-hdmi
34          - allwinner,sun8i-r40-dw-hdmi
35          - allwinner,sun50i-a64-dw-hdmi
36        - const: allwinner,sun8i-a83t-dw-hdmi
37
38  reg:
39    maxItems: 1
40
41  reg-io-width:
42    const: 1
43
44  interrupts:
45    maxItems: 1
46
47  clocks:
48    minItems: 3
49    maxItems: 6
50    items:
51      - description: Bus Clock
52      - description: Register Clock
53      - description: TMDS Clock
54      - description: HDMI CEC Clock
55      - description: HDCP Clock
56      - description: HDCP Bus Clock
57
58  clock-names:
59    minItems: 3
60    maxItems: 6
61    items:
62      - const: iahb
63      - const: isfr
64      - const: tmds
65      - const: cec
66      - const: hdcp
67      - const: hdcp-bus
68
69  resets:
70    minItems: 1
71    maxItems: 2
72    items:
73      - description: HDMI Controller Reset
74      - description: HDCP Reset
75
76  reset-names:
77    minItems: 1
78    maxItems: 2
79    items:
80      - const: ctrl
81      - const: hdcp
82
83  phys:
84    maxItems: 1
85    description:
86      Phandle to the DWC HDMI PHY.
87
88  phy-names:
89    const: phy
90
91  hvcc-supply:
92    description:
93      The VCC power supply of the controller
94
95  ports:
96    type: object
97    description: |
98      A ports node with endpoint definitions as defined in
99      Documentation/devicetree/bindings/media/video-interfaces.txt.
100
101    properties:
102      "#address-cells":
103        const: 1
104
105      "#size-cells":
106        const: 0
107
108      port@0:
109        type: object
110        description: |
111          Input endpoints of the controller. Usually the associated
112          TCON.
113
114      port@1:
115        type: object
116        description: |
117          Output endpoints of the controller. Usually an HDMI
118          connector.
119
120    required:
121      - "#address-cells"
122      - "#size-cells"
123      - port@0
124      - port@1
125
126    additionalProperties: false
127
128required:
129  - compatible
130  - reg
131  - reg-io-width
132  - interrupts
133  - clocks
134  - clock-names
135  - resets
136  - reset-names
137  - phys
138  - phy-names
139  - ports
140
141if:
142  properties:
143    compatible:
144      contains:
145        enum:
146          - allwinner,sun50i-h6-dw-hdmi
147
148then:
149  properties:
150    clocks:
151      minItems: 6
152
153    clock-names:
154      minItems: 6
155
156    resets:
157      minItems: 2
158
159    reset-names:
160      minItems: 2
161
162
163additionalProperties: false
164
165examples:
166  - |
167    #include <dt-bindings/interrupt-controller/arm-gic.h>
168
169    /*
170     * This comes from the clock/sun8i-a83t-ccu.h and
171     * reset/sun8i-a83t-ccu.h headers, but we can't include them since
172     * it would trigger a bunch of warnings for redefinitions of
173     * symbols with the other example.
174     */
175    #define CLK_BUS_HDMI	39
176    #define CLK_HDMI		93
177    #define CLK_HDMI_SLOW	94
178    #define RST_BUS_HDMI1	26
179
180    hdmi@1ee0000 {
181        compatible = "allwinner,sun8i-a83t-dw-hdmi";
182        reg = <0x01ee0000 0x10000>;
183        reg-io-width = <1>;
184        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
185        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
186                 <&ccu CLK_HDMI>;
187        clock-names = "iahb", "isfr", "tmds";
188        resets = <&ccu RST_BUS_HDMI1>;
189        reset-names = "ctrl";
190        phys = <&hdmi_phy>;
191        phy-names = "phy";
192        pinctrl-names = "default";
193        pinctrl-0 = <&hdmi_pins>;
194        status = "disabled";
195
196        ports {
197            #address-cells = <1>;
198            #size-cells = <0>;
199
200            port@0 {
201                reg = <0>;
202
203                endpoint {
204                    remote-endpoint = <&tcon1_out_hdmi>;
205                };
206            };
207
208            port@1 {
209                reg = <1>;
210            };
211        };
212    };
213
214    /* Cleanup after ourselves */
215    #undef CLK_BUS_HDMI
216    #undef CLK_HDMI
217    #undef CLK_HDMI_SLOW
218
219  - |
220    #include <dt-bindings/interrupt-controller/arm-gic.h>
221
222    /*
223     * This comes from the clock/sun50i-h6-ccu.h and
224     * reset/sun50i-h6-ccu.h headers, but we can't include them since
225     * it would trigger a bunch of warnings for redefinitions of
226     * symbols with the other example.
227     */
228    #define CLK_BUS_HDMI	126
229    #define CLK_BUS_HDCP	137
230    #define CLK_HDMI		123
231    #define CLK_HDMI_SLOW	124
232    #define CLK_HDMI_CEC	125
233    #define CLK_HDCP		136
234    #define RST_BUS_HDMI_SUB	57
235    #define RST_BUS_HDCP	62
236
237    hdmi@6000000 {
238        compatible = "allwinner,sun50i-h6-dw-hdmi";
239        reg = <0x06000000 0x10000>;
240        reg-io-width = <1>;
241        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
242        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
243                 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
244                 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
245        clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
246                      "hdcp-bus";
247        resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
248        reset-names = "ctrl", "hdcp";
249        phys = <&hdmi_phy>;
250        phy-names = "phy";
251        pinctrl-names = "default";
252        pinctrl-0 = <&hdmi_pins>;
253        status = "disabled";
254
255        ports {
256            #address-cells = <1>;
257            #size-cells = <0>;
258
259            port@0 {
260                reg = <0>;
261
262                endpoint {
263                    remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
264                };
265            };
266
267            port@1 {
268                reg = <1>;
269            };
270        };
271    };
272
273...
274