1f5a98bfeSMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2f5a98bfeSMaxime Ripard%YAML 1.2 3f5a98bfeSMaxime Ripard--- 4f5a98bfeSMaxime Ripard$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml# 5f5a98bfeSMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6f5a98bfeSMaxime Ripard 7f5a98bfeSMaxime Ripardtitle: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings 8f5a98bfeSMaxime Ripard 9f5a98bfeSMaxime Riparddescription: | 10f5a98bfeSMaxime Ripard The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller 11f5a98bfeSMaxime Ripard IP with Allwinner\'s own PHY IP. It supports audio and video outputs 12f5a98bfeSMaxime Ripard and CEC. 13f5a98bfeSMaxime Ripard 14f5a98bfeSMaxime Ripard These DT bindings follow the Synopsys DWC HDMI TX bindings defined 15f5a98bfeSMaxime Ripard in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with 16f5a98bfeSMaxime Ripard the following device-specific properties. 17f5a98bfeSMaxime Ripard 18f5a98bfeSMaxime Ripardmaintainers: 19f5a98bfeSMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 20f5a98bfeSMaxime Ripard - Maxime Ripard <mripard@kernel.org> 21f5a98bfeSMaxime Ripard 22f5a98bfeSMaxime Ripardproperties: 23f5a98bfeSMaxime Ripard "#phy-cells": 24f5a98bfeSMaxime Ripard const: 0 25f5a98bfeSMaxime Ripard 26f5a98bfeSMaxime Ripard compatible: 27f5a98bfeSMaxime Ripard oneOf: 28f5a98bfeSMaxime Ripard - const: allwinner,sun8i-a83t-dw-hdmi 29f5a98bfeSMaxime Ripard - const: allwinner,sun50i-h6-dw-hdmi 30f5a98bfeSMaxime Ripard 31f5a98bfeSMaxime Ripard - items: 32f5a98bfeSMaxime Ripard - enum: 33f5a98bfeSMaxime Ripard - allwinner,sun8i-h3-dw-hdmi 34f5a98bfeSMaxime Ripard - allwinner,sun8i-r40-dw-hdmi 35f5a98bfeSMaxime Ripard - allwinner,sun50i-a64-dw-hdmi 36f5a98bfeSMaxime Ripard - const: allwinner,sun8i-a83t-dw-hdmi 37f5a98bfeSMaxime Ripard 38f5a98bfeSMaxime Ripard reg: 39f5a98bfeSMaxime Ripard maxItems: 1 40f5a98bfeSMaxime Ripard 41f5a98bfeSMaxime Ripard reg-io-width: 42f5a98bfeSMaxime Ripard const: 1 43f5a98bfeSMaxime Ripard 44f5a98bfeSMaxime Ripard interrupts: 45f5a98bfeSMaxime Ripard maxItems: 1 46f5a98bfeSMaxime Ripard 47f5a98bfeSMaxime Ripard clocks: 48f5a98bfeSMaxime Ripard minItems: 3 49f5a98bfeSMaxime Ripard maxItems: 6 50f5a98bfeSMaxime Ripard items: 51f5a98bfeSMaxime Ripard - description: Bus Clock 52f5a98bfeSMaxime Ripard - description: Register Clock 53f5a98bfeSMaxime Ripard - description: TMDS Clock 54f5a98bfeSMaxime Ripard - description: HDMI CEC Clock 55f5a98bfeSMaxime Ripard - description: HDCP Clock 56f5a98bfeSMaxime Ripard - description: HDCP Bus Clock 57f5a98bfeSMaxime Ripard 58f5a98bfeSMaxime Ripard clock-names: 59f5a98bfeSMaxime Ripard minItems: 3 60f5a98bfeSMaxime Ripard maxItems: 6 61f5a98bfeSMaxime Ripard items: 62f5a98bfeSMaxime Ripard - const: iahb 63f5a98bfeSMaxime Ripard - const: isfr 64f5a98bfeSMaxime Ripard - const: tmds 65f5a98bfeSMaxime Ripard - const: cec 66f5a98bfeSMaxime Ripard - const: hdcp 67f5a98bfeSMaxime Ripard - const: hdcp-bus 68f5a98bfeSMaxime Ripard 69f5a98bfeSMaxime Ripard resets: 70f5a98bfeSMaxime Ripard minItems: 1 71f5a98bfeSMaxime Ripard maxItems: 2 72f5a98bfeSMaxime Ripard items: 73f5a98bfeSMaxime Ripard - description: HDMI Controller Reset 74f5a98bfeSMaxime Ripard - description: HDCP Reset 75f5a98bfeSMaxime Ripard 76f5a98bfeSMaxime Ripard reset-names: 77f5a98bfeSMaxime Ripard minItems: 1 78f5a98bfeSMaxime Ripard maxItems: 2 79f5a98bfeSMaxime Ripard items: 80f5a98bfeSMaxime Ripard - const: ctrl 81f5a98bfeSMaxime Ripard - const: hdcp 82f5a98bfeSMaxime Ripard 83f5a98bfeSMaxime Ripard phys: 84f5a98bfeSMaxime Ripard maxItems: 1 85f5a98bfeSMaxime Ripard description: 86f5a98bfeSMaxime Ripard Phandle to the DWC HDMI PHY. 87f5a98bfeSMaxime Ripard 88f5a98bfeSMaxime Ripard phy-names: 89f5a98bfeSMaxime Ripard const: phy 90f5a98bfeSMaxime Ripard 91f5a98bfeSMaxime Ripard hvcc-supply: 92f5a98bfeSMaxime Ripard description: 93f5a98bfeSMaxime Ripard The VCC power supply of the controller 94f5a98bfeSMaxime Ripard 95f5a98bfeSMaxime Ripard ports: 96f5a98bfeSMaxime Ripard type: object 97f5a98bfeSMaxime Ripard description: | 98f5a98bfeSMaxime Ripard A ports node with endpoint definitions as defined in 99f5a98bfeSMaxime Ripard Documentation/devicetree/bindings/media/video-interfaces.txt. 100f5a98bfeSMaxime Ripard 101f5a98bfeSMaxime Ripard properties: 102f5a98bfeSMaxime Ripard "#address-cells": 103f5a98bfeSMaxime Ripard const: 1 104f5a98bfeSMaxime Ripard 105f5a98bfeSMaxime Ripard "#size-cells": 106f5a98bfeSMaxime Ripard const: 0 107f5a98bfeSMaxime Ripard 108f5a98bfeSMaxime Ripard port@0: 109f5a98bfeSMaxime Ripard type: object 110f5a98bfeSMaxime Ripard description: | 111f5a98bfeSMaxime Ripard Input endpoints of the controller. Usually the associated 112f5a98bfeSMaxime Ripard TCON. 113f5a98bfeSMaxime Ripard 114f5a98bfeSMaxime Ripard port@1: 115f5a98bfeSMaxime Ripard type: object 116f5a98bfeSMaxime Ripard description: | 117f5a98bfeSMaxime Ripard Output endpoints of the controller. Usually an HDMI 118f5a98bfeSMaxime Ripard connector. 119f5a98bfeSMaxime Ripard 120f5a98bfeSMaxime Ripard required: 121f5a98bfeSMaxime Ripard - "#address-cells" 122f5a98bfeSMaxime Ripard - "#size-cells" 123f5a98bfeSMaxime Ripard - port@0 124f5a98bfeSMaxime Ripard - port@1 125f5a98bfeSMaxime Ripard 126f5a98bfeSMaxime Ripard additionalProperties: false 127f5a98bfeSMaxime Ripard 128f5a98bfeSMaxime Ripardrequired: 129f5a98bfeSMaxime Ripard - compatible 130f5a98bfeSMaxime Ripard - reg 131f5a98bfeSMaxime Ripard - reg-io-width 132f5a98bfeSMaxime Ripard - interrupts 133f5a98bfeSMaxime Ripard - clocks 134f5a98bfeSMaxime Ripard - clock-names 135f5a98bfeSMaxime Ripard - resets 136f5a98bfeSMaxime Ripard - reset-names 137f5a98bfeSMaxime Ripard - phys 138f5a98bfeSMaxime Ripard - phy-names 139f5a98bfeSMaxime Ripard - ports 140f5a98bfeSMaxime Ripard 141f5a98bfeSMaxime Ripardif: 142f5a98bfeSMaxime Ripard properties: 143f5a98bfeSMaxime Ripard compatible: 144f5a98bfeSMaxime Ripard contains: 145f5a98bfeSMaxime Ripard enum: 146f5a98bfeSMaxime Ripard - allwinner,sun50i-h6-dw-hdmi 147f5a98bfeSMaxime Ripard 148f5a98bfeSMaxime Ripardthen: 149f5a98bfeSMaxime Ripard properties: 150f5a98bfeSMaxime Ripard clocks: 151f5a98bfeSMaxime Ripard minItems: 6 152f5a98bfeSMaxime Ripard 153f5a98bfeSMaxime Ripard clock-names: 154f5a98bfeSMaxime Ripard minItems: 6 155f5a98bfeSMaxime Ripard 156f5a98bfeSMaxime Ripard resets: 157f5a98bfeSMaxime Ripard minItems: 2 158f5a98bfeSMaxime Ripard 159f5a98bfeSMaxime Ripard reset-names: 160f5a98bfeSMaxime Ripard minItems: 2 161f5a98bfeSMaxime Ripard 162f5a98bfeSMaxime Ripard 163f5a98bfeSMaxime RipardadditionalProperties: false 164f5a98bfeSMaxime Ripard 165f5a98bfeSMaxime Ripardexamples: 166f5a98bfeSMaxime Ripard - | 167f5a98bfeSMaxime Ripard #include <dt-bindings/interrupt-controller/arm-gic.h> 168f5a98bfeSMaxime Ripard 169f5a98bfeSMaxime Ripard /* 170f5a98bfeSMaxime Ripard * This comes from the clock/sun8i-a83t-ccu.h and 171f5a98bfeSMaxime Ripard * reset/sun8i-a83t-ccu.h headers, but we can't include them since 172f5a98bfeSMaxime Ripard * it would trigger a bunch of warnings for redefinitions of 173f5a98bfeSMaxime Ripard * symbols with the other example. 174f5a98bfeSMaxime Ripard */ 175f5a98bfeSMaxime Ripard #define CLK_BUS_HDMI 39 176f5a98bfeSMaxime Ripard #define CLK_HDMI 93 177f5a98bfeSMaxime Ripard #define CLK_HDMI_SLOW 94 178f5a98bfeSMaxime Ripard #define RST_BUS_HDMI1 26 179f5a98bfeSMaxime Ripard 180f5a98bfeSMaxime Ripard hdmi@1ee0000 { 181f5a98bfeSMaxime Ripard compatible = "allwinner,sun8i-a83t-dw-hdmi"; 182f5a98bfeSMaxime Ripard reg = <0x01ee0000 0x10000>; 183f5a98bfeSMaxime Ripard reg-io-width = <1>; 184f5a98bfeSMaxime Ripard interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 185f5a98bfeSMaxime Ripard clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 186f5a98bfeSMaxime Ripard <&ccu CLK_HDMI>; 187f5a98bfeSMaxime Ripard clock-names = "iahb", "isfr", "tmds"; 188f5a98bfeSMaxime Ripard resets = <&ccu RST_BUS_HDMI1>; 189f5a98bfeSMaxime Ripard reset-names = "ctrl"; 190f5a98bfeSMaxime Ripard phys = <&hdmi_phy>; 191f5a98bfeSMaxime Ripard phy-names = "phy"; 192f5a98bfeSMaxime Ripard pinctrl-names = "default"; 193f5a98bfeSMaxime Ripard pinctrl-0 = <&hdmi_pins>; 194f5a98bfeSMaxime Ripard status = "disabled"; 195f5a98bfeSMaxime Ripard 196f5a98bfeSMaxime Ripard ports { 197f5a98bfeSMaxime Ripard #address-cells = <1>; 198f5a98bfeSMaxime Ripard #size-cells = <0>; 199f5a98bfeSMaxime Ripard 200f5a98bfeSMaxime Ripard port@0 { 201f5a98bfeSMaxime Ripard reg = <0>; 202f5a98bfeSMaxime Ripard 203f5a98bfeSMaxime Ripard endpoint { 204f5a98bfeSMaxime Ripard remote-endpoint = <&tcon1_out_hdmi>; 205f5a98bfeSMaxime Ripard }; 206f5a98bfeSMaxime Ripard }; 207f5a98bfeSMaxime Ripard 208f5a98bfeSMaxime Ripard port@1 { 209f5a98bfeSMaxime Ripard reg = <1>; 210f5a98bfeSMaxime Ripard }; 211f5a98bfeSMaxime Ripard }; 212f5a98bfeSMaxime Ripard }; 213f5a98bfeSMaxime Ripard 214f5a98bfeSMaxime Ripard /* Cleanup after ourselves */ 215f5a98bfeSMaxime Ripard #undef CLK_BUS_HDMI 216f5a98bfeSMaxime Ripard #undef CLK_HDMI 217f5a98bfeSMaxime Ripard #undef CLK_HDMI_SLOW 218f5a98bfeSMaxime Ripard 219f5a98bfeSMaxime Ripard - | 220f5a98bfeSMaxime Ripard #include <dt-bindings/interrupt-controller/arm-gic.h> 221f5a98bfeSMaxime Ripard 222f5a98bfeSMaxime Ripard /* 223f5a98bfeSMaxime Ripard * This comes from the clock/sun50i-h6-ccu.h and 224f5a98bfeSMaxime Ripard * reset/sun50i-h6-ccu.h headers, but we can't include them since 225f5a98bfeSMaxime Ripard * it would trigger a bunch of warnings for redefinitions of 226f5a98bfeSMaxime Ripard * symbols with the other example. 227f5a98bfeSMaxime Ripard */ 228f5a98bfeSMaxime Ripard #define CLK_BUS_HDMI 126 229f5a98bfeSMaxime Ripard #define CLK_BUS_HDCP 137 230f5a98bfeSMaxime Ripard #define CLK_HDMI 123 231f5a98bfeSMaxime Ripard #define CLK_HDMI_SLOW 124 232f5a98bfeSMaxime Ripard #define CLK_HDMI_CEC 125 233f5a98bfeSMaxime Ripard #define CLK_HDCP 136 234f5a98bfeSMaxime Ripard #define RST_BUS_HDMI_SUB 57 235f5a98bfeSMaxime Ripard #define RST_BUS_HDCP 62 236f5a98bfeSMaxime Ripard 237f5a98bfeSMaxime Ripard hdmi@6000000 { 238f5a98bfeSMaxime Ripard compatible = "allwinner,sun50i-h6-dw-hdmi"; 239f5a98bfeSMaxime Ripard reg = <0x06000000 0x10000>; 240f5a98bfeSMaxime Ripard reg-io-width = <1>; 241f5a98bfeSMaxime Ripard interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 242f5a98bfeSMaxime Ripard clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 243f5a98bfeSMaxime Ripard <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 244f5a98bfeSMaxime Ripard <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 245f5a98bfeSMaxime Ripard clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 246f5a98bfeSMaxime Ripard "hdcp-bus"; 247f5a98bfeSMaxime Ripard resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 248f5a98bfeSMaxime Ripard reset-names = "ctrl", "hdcp"; 249f5a98bfeSMaxime Ripard phys = <&hdmi_phy>; 250f5a98bfeSMaxime Ripard phy-names = "phy"; 251f5a98bfeSMaxime Ripard pinctrl-names = "default"; 252f5a98bfeSMaxime Ripard pinctrl-0 = <&hdmi_pins>; 253f5a98bfeSMaxime Ripard status = "disabled"; 254f5a98bfeSMaxime Ripard 255f5a98bfeSMaxime Ripard ports { 256f5a98bfeSMaxime Ripard #address-cells = <1>; 257f5a98bfeSMaxime Ripard #size-cells = <0>; 258f5a98bfeSMaxime Ripard 259f5a98bfeSMaxime Ripard port@0 { 260f5a98bfeSMaxime Ripard reg = <0>; 261f5a98bfeSMaxime Ripard 262f5a98bfeSMaxime Ripard endpoint { 263f5a98bfeSMaxime Ripard remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 264f5a98bfeSMaxime Ripard }; 265f5a98bfeSMaxime Ripard }; 266f5a98bfeSMaxime Ripard 267f5a98bfeSMaxime Ripard port@1 { 268f5a98bfeSMaxime Ripard reg = <1>; 269f5a98bfeSMaxime Ripard }; 270f5a98bfeSMaxime Ripard }; 271f5a98bfeSMaxime Ripard }; 272f5a98bfeSMaxime Ripard 273f5a98bfeSMaxime Ripard... 274