1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A31 MIPI-DSI Controller 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13properties: 14 compatible: 15 enum: 16 - allwinner,sun6i-a31-mipi-dsi 17 - allwinner,sun50i-a64-mipi-dsi 18 19 reg: 20 maxItems: 1 21 22 interrupts: 23 maxItems: 1 24 25 clocks: 26 minItems: 1 27 items: 28 - description: Bus Clock 29 - description: Module Clock 30 31 clock-names: 32 items: 33 - const: bus 34 - const: mod 35 36 resets: 37 maxItems: 1 38 39 vcc-dsi-supply: 40 description: VCC-DSI power supply of the DSI encoder 41 42 phys: 43 maxItems: 1 44 45 phy-names: 46 const: dphy 47 48 port: 49 $ref: /schemas/graph.yaml#/properties/port 50 description: 51 The port should be the input endpoint, usually coming from the 52 associated TCON. 53 54required: 55 - compatible 56 - reg 57 - interrupts 58 - clocks 59 - phys 60 - phy-names 61 - resets 62 - vcc-dsi-supply 63 - port 64 65allOf: 66 - $ref: dsi-controller.yaml# 67 - if: 68 properties: 69 compatible: 70 contains: 71 const: allwinner,sun6i-a31-mipi-dsi 72 73 then: 74 properties: 75 clocks: 76 minItems: 2 77 78 required: 79 - clock-names 80 81 else: 82 properties: 83 clocks: 84 maxItems: 1 85 86unevaluatedProperties: false 87 88examples: 89 - | 90 dsi0: dsi@1ca0000 { 91 compatible = "allwinner,sun6i-a31-mipi-dsi"; 92 reg = <0x01ca0000 0x1000>; 93 interrupts = <0 89 4>; 94 clocks = <&ccu 23>, <&ccu 96>; 95 clock-names = "bus", "mod"; 96 resets = <&ccu 4>; 97 phys = <&dphy0>; 98 phy-names = "dphy"; 99 vcc-dsi-supply = <®_dcdc1>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 panel@0 { 104 compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; 105 reg = <0>; 106 power-supply = <®_display>; 107 reset-gpios = <&r_pio 0 5 1>; /* PL05 */ 108 backlight = <&pwm_bl>; 109 }; 110 111 port { 112 dsi0_in_tcon0: endpoint { 113 remote-endpoint = <&tcon0_out_dsi0>; 114 }; 115 }; 116 }; 117 118... 119