1Tegra124 CPU frequency scaling driver bindings
2----------------------------------------------
3
4Both required and optional properties listed below must be defined
5under node /cpus/cpu@0.
6
7Required properties:
8- clocks: Must contain an entry for each entry in clock-names.
9  See ../clocks/clock-bindings.txt for details.
10- clock-names: Must include the following entries:
11  - cpu_g: Clock mux for the fast CPU cluster.
12  - cpu_lp: Clock mux for the low-power CPU cluster.
13  - pll_x: Fast PLL clocksource.
14  - pll_p: Auxiliary PLL used during fast PLL rate changes.
15  - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
16- vdd-cpu-supply: Regulator for CPU voltage
17
18Optional properties:
19- clock-latency: Specify the possible maximum transition latency for clock,
20  in unit of nanoseconds.
21
22Example:
23--------
24cpus {
25	#address-cells = <1>;
26	#size-cells = <0>;
27
28	cpu@0 {
29		device_type = "cpu";
30		compatible = "arm,cortex-a15";
31		reg = <0>;
32
33		clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
34			 <&tegra_car TEGRA124_CLK_CCLK_LP>,
35			 <&tegra_car TEGRA124_CLK_PLL_X>,
36			 <&tegra_car TEGRA124_CLK_PLL_P>,
37			 <&dfll>;
38		clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
39		clock-latency = <300000>;
40		vdd-cpu-supply: <&vdd_cpu>;
41	};
42
43	<...>
44};
45