142099322SDeepak SikriSPEAr cpufreq driver 242099322SDeepak Sikri------------------- 342099322SDeepak Sikri 442099322SDeepak SikriSPEAr SoC cpufreq driver for CPU frequency scaling. 542099322SDeepak SikriIt supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems 642099322SDeepak Sikriwhich share clock across all CPUs. 742099322SDeepak Sikri 842099322SDeepak SikriRequired properties: 942099322SDeepak Sikri- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the 1042099322SDeepak Sikri increasing order. 1142099322SDeepak Sikri 1242099322SDeepak SikriOptional properties: 1342099322SDeepak Sikri- clock-latency: Specify the possible maximum transition latency for clock, in 1442099322SDeepak Sikri unit of nanoseconds. 1542099322SDeepak Sikri 1642099322SDeepak SikriBoth required and optional properties listed above must be defined under node 1742099322SDeepak Sikri/cpus/cpu@0. 1842099322SDeepak Sikri 1942099322SDeepak SikriExamples: 2042099322SDeepak Sikri-------- 2142099322SDeepak Sikricpus { 2242099322SDeepak Sikri 2342099322SDeepak Sikri <...> 2442099322SDeepak Sikri 2542099322SDeepak Sikri cpu@0 { 2642099322SDeepak Sikri compatible = "arm,cortex-a9"; 2742099322SDeepak Sikri reg = <0>; 2842099322SDeepak Sikri 2942099322SDeepak Sikri <...> 3042099322SDeepak Sikri 3142099322SDeepak Sikri cpufreq_tbl = < 166000 3242099322SDeepak Sikri 200000 3342099322SDeepak Sikri 250000 3442099322SDeepak Sikri 300000 3542099322SDeepak Sikri 400000 3642099322SDeepak Sikri 500000 3742099322SDeepak Sikri 600000 >; 3842099322SDeepak Sikri }; 3942099322SDeepak Sikri 4042099322SDeepak Sikri <...> 4142099322SDeepak Sikri 4242099322SDeepak Sikri}; 43