1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - const: qcom,cpufreq-hw
24
25      - description: v2 of CPUFREQ HW (EPSS)
26        items:
27          - enum:
28              - qcom,qdu1000-cpufreq-epss
29              - qcom,sm6375-cpufreq-epss
30              - qcom,sm8250-cpufreq-epss
31          - const: qcom,cpufreq-epss
32
33  reg:
34    minItems: 2
35    items:
36      - description: Frequency domain 0 register region
37      - description: Frequency domain 1 register region
38      - description: Frequency domain 2 register region
39
40  reg-names:
41    minItems: 2
42    items:
43      - const: freq-domain0
44      - const: freq-domain1
45      - const: freq-domain2
46
47  clocks:
48    items:
49      - description: XO Clock
50      - description: GPLL0 Clock
51
52  clock-names:
53    items:
54      - const: xo
55      - const: alternate
56
57  interrupts:
58    minItems: 1
59    maxItems: 3
60
61  interrupt-names:
62    minItems: 1
63    items:
64      - const: dcvsh-irq-0
65      - const: dcvsh-irq-1
66      - const: dcvsh-irq-2
67
68  '#freq-domain-cells':
69    const: 1
70
71  '#clock-cells':
72    const: 1
73
74required:
75  - compatible
76  - reg
77  - clocks
78  - clock-names
79  - '#freq-domain-cells'
80
81additionalProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
86    #include <dt-bindings/clock/qcom,rpmh.h>
87
88    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
89    // switch DCVS state together.
90    cpus {
91      #address-cells = <2>;
92      #size-cells = <0>;
93
94      CPU0: cpu@0 {
95        device_type = "cpu";
96        compatible = "qcom,kryo385";
97        reg = <0x0 0x0>;
98        enable-method = "psci";
99        next-level-cache = <&L2_0>;
100        qcom,freq-domain = <&cpufreq_hw 0>;
101        clocks = <&cpufreq_hw 0>;
102        L2_0: l2-cache {
103          compatible = "cache";
104          cache-unified;
105          cache-level = <2>;
106          next-level-cache = <&L3_0>;
107          L3_0: l3-cache {
108            compatible = "cache";
109            cache-unified;
110            cache-level = <3>;
111          };
112        };
113      };
114
115      CPU1: cpu@100 {
116        device_type = "cpu";
117        compatible = "qcom,kryo385";
118        reg = <0x0 0x100>;
119        enable-method = "psci";
120        next-level-cache = <&L2_100>;
121        qcom,freq-domain = <&cpufreq_hw 0>;
122        clocks = <&cpufreq_hw 0>;
123        L2_100: l2-cache {
124          compatible = "cache";
125          cache-unified;
126          cache-level = <2>;
127          next-level-cache = <&L3_0>;
128        };
129      };
130
131      CPU2: cpu@200 {
132        device_type = "cpu";
133        compatible = "qcom,kryo385";
134        reg = <0x0 0x200>;
135        enable-method = "psci";
136        next-level-cache = <&L2_200>;
137        qcom,freq-domain = <&cpufreq_hw 0>;
138        clocks = <&cpufreq_hw 0>;
139        L2_200: l2-cache {
140          compatible = "cache";
141          cache-unified;
142          cache-level = <2>;
143          next-level-cache = <&L3_0>;
144        };
145      };
146
147      CPU3: cpu@300 {
148        device_type = "cpu";
149        compatible = "qcom,kryo385";
150        reg = <0x0 0x300>;
151        enable-method = "psci";
152        next-level-cache = <&L2_300>;
153        qcom,freq-domain = <&cpufreq_hw 0>;
154        clocks = <&cpufreq_hw 0>;
155        L2_300: l2-cache {
156          compatible = "cache";
157          cache-unified;
158          cache-level = <2>;
159          next-level-cache = <&L3_0>;
160        };
161      };
162
163      CPU4: cpu@400 {
164        device_type = "cpu";
165        compatible = "qcom,kryo385";
166        reg = <0x0 0x400>;
167        enable-method = "psci";
168        next-level-cache = <&L2_400>;
169        qcom,freq-domain = <&cpufreq_hw 1>;
170        clocks = <&cpufreq_hw 1>;
171        L2_400: l2-cache {
172          compatible = "cache";
173          cache-unified;
174          cache-level = <2>;
175          next-level-cache = <&L3_0>;
176        };
177      };
178
179      CPU5: cpu@500 {
180        device_type = "cpu";
181        compatible = "qcom,kryo385";
182        reg = <0x0 0x500>;
183        enable-method = "psci";
184        next-level-cache = <&L2_500>;
185        qcom,freq-domain = <&cpufreq_hw 1>;
186        clocks = <&cpufreq_hw 1>;
187        L2_500: l2-cache {
188          compatible = "cache";
189          cache-unified;
190          cache-level = <2>;
191          next-level-cache = <&L3_0>;
192        };
193      };
194
195      CPU6: cpu@600 {
196        device_type = "cpu";
197        compatible = "qcom,kryo385";
198        reg = <0x0 0x600>;
199        enable-method = "psci";
200        next-level-cache = <&L2_600>;
201        qcom,freq-domain = <&cpufreq_hw 1>;
202        clocks = <&cpufreq_hw 1>;
203        L2_600: l2-cache {
204          compatible = "cache";
205          cache-unified;
206          cache-level = <2>;
207          next-level-cache = <&L3_0>;
208        };
209      };
210
211      CPU7: cpu@700 {
212        device_type = "cpu";
213        compatible = "qcom,kryo385";
214        reg = <0x0 0x700>;
215        enable-method = "psci";
216        next-level-cache = <&L2_700>;
217        qcom,freq-domain = <&cpufreq_hw 1>;
218        clocks = <&cpufreq_hw 1>;
219        L2_700: l2-cache {
220          compatible = "cache";
221          cache-unified;
222          cache-level = <2>;
223          next-level-cache = <&L3_0>;
224        };
225      };
226    };
227
228    soc {
229      #address-cells = <1>;
230      #size-cells = <1>;
231
232      cpufreq@17d43000 {
233        compatible = "qcom,cpufreq-hw";
234        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
235        reg-names = "freq-domain0", "freq-domain1";
236
237        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
238        clock-names = "xo", "alternate";
239
240        #freq-domain-cells = <1>;
241        #clock-cells = <1>;
242      };
243    };
244...
245