1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - const: qcom,cpufreq-hw
24
25      - description: v2 of CPUFREQ HW (EPSS)
26        items:
27          - enum:
28              - qcom,qdu1000-cpufreq-epss
29              - qcom,sm6375-cpufreq-epss
30              - qcom,sm8250-cpufreq-epss
31          - const: qcom,cpufreq-epss
32
33  reg:
34    minItems: 2
35    items:
36      - description: Frequency domain 0 register region
37      - description: Frequency domain 1 register region
38      - description: Frequency domain 2 register region
39
40  reg-names:
41    minItems: 2
42    items:
43      - const: freq-domain0
44      - const: freq-domain1
45      - const: freq-domain2
46
47  clocks:
48    items:
49      - description: XO Clock
50      - description: GPLL0 Clock
51
52  clock-names:
53    items:
54      - const: xo
55      - const: alternate
56
57  '#freq-domain-cells':
58    const: 1
59
60  '#clock-cells':
61    const: 1
62
63required:
64  - compatible
65  - reg
66  - clocks
67  - clock-names
68  - '#freq-domain-cells'
69
70additionalProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
75    #include <dt-bindings/clock/qcom,rpmh.h>
76
77    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
78    // switch DCVS state together.
79    cpus {
80      #address-cells = <2>;
81      #size-cells = <0>;
82
83      CPU0: cpu@0 {
84        device_type = "cpu";
85        compatible = "qcom,kryo385";
86        reg = <0x0 0x0>;
87        enable-method = "psci";
88        next-level-cache = <&L2_0>;
89        qcom,freq-domain = <&cpufreq_hw 0>;
90        clocks = <&cpufreq_hw 0>;
91        L2_0: l2-cache {
92          compatible = "cache";
93          cache-unified;
94          cache-level = <2>;
95          next-level-cache = <&L3_0>;
96          L3_0: l3-cache {
97            compatible = "cache";
98            cache-unified;
99            cache-level = <3>;
100          };
101        };
102      };
103
104      CPU1: cpu@100 {
105        device_type = "cpu";
106        compatible = "qcom,kryo385";
107        reg = <0x0 0x100>;
108        enable-method = "psci";
109        next-level-cache = <&L2_100>;
110        qcom,freq-domain = <&cpufreq_hw 0>;
111        clocks = <&cpufreq_hw 0>;
112        L2_100: l2-cache {
113          compatible = "cache";
114          cache-unified;
115          cache-level = <2>;
116          next-level-cache = <&L3_0>;
117        };
118      };
119
120      CPU2: cpu@200 {
121        device_type = "cpu";
122        compatible = "qcom,kryo385";
123        reg = <0x0 0x200>;
124        enable-method = "psci";
125        next-level-cache = <&L2_200>;
126        qcom,freq-domain = <&cpufreq_hw 0>;
127        clocks = <&cpufreq_hw 0>;
128        L2_200: l2-cache {
129          compatible = "cache";
130          cache-unified;
131          cache-level = <2>;
132          next-level-cache = <&L3_0>;
133        };
134      };
135
136      CPU3: cpu@300 {
137        device_type = "cpu";
138        compatible = "qcom,kryo385";
139        reg = <0x0 0x300>;
140        enable-method = "psci";
141        next-level-cache = <&L2_300>;
142        qcom,freq-domain = <&cpufreq_hw 0>;
143        clocks = <&cpufreq_hw 0>;
144        L2_300: l2-cache {
145          compatible = "cache";
146          cache-unified;
147          cache-level = <2>;
148          next-level-cache = <&L3_0>;
149        };
150      };
151
152      CPU4: cpu@400 {
153        device_type = "cpu";
154        compatible = "qcom,kryo385";
155        reg = <0x0 0x400>;
156        enable-method = "psci";
157        next-level-cache = <&L2_400>;
158        qcom,freq-domain = <&cpufreq_hw 1>;
159        clocks = <&cpufreq_hw 1>;
160        L2_400: l2-cache {
161          compatible = "cache";
162          cache-unified;
163          cache-level = <2>;
164          next-level-cache = <&L3_0>;
165        };
166      };
167
168      CPU5: cpu@500 {
169        device_type = "cpu";
170        compatible = "qcom,kryo385";
171        reg = <0x0 0x500>;
172        enable-method = "psci";
173        next-level-cache = <&L2_500>;
174        qcom,freq-domain = <&cpufreq_hw 1>;
175        clocks = <&cpufreq_hw 1>;
176        L2_500: l2-cache {
177          compatible = "cache";
178          cache-unified;
179          cache-level = <2>;
180          next-level-cache = <&L3_0>;
181        };
182      };
183
184      CPU6: cpu@600 {
185        device_type = "cpu";
186        compatible = "qcom,kryo385";
187        reg = <0x0 0x600>;
188        enable-method = "psci";
189        next-level-cache = <&L2_600>;
190        qcom,freq-domain = <&cpufreq_hw 1>;
191        clocks = <&cpufreq_hw 1>;
192        L2_600: l2-cache {
193          compatible = "cache";
194          cache-unified;
195          cache-level = <2>;
196          next-level-cache = <&L3_0>;
197        };
198      };
199
200      CPU7: cpu@700 {
201        device_type = "cpu";
202        compatible = "qcom,kryo385";
203        reg = <0x0 0x700>;
204        enable-method = "psci";
205        next-level-cache = <&L2_700>;
206        qcom,freq-domain = <&cpufreq_hw 1>;
207        clocks = <&cpufreq_hw 1>;
208        L2_700: l2-cache {
209          compatible = "cache";
210          cache-unified;
211          cache-level = <2>;
212          next-level-cache = <&L3_0>;
213        };
214      };
215    };
216
217    soc {
218      #address-cells = <1>;
219      #size-cells = <1>;
220
221      cpufreq@17d43000 {
222        compatible = "qcom,cpufreq-hw";
223        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
224        reg-names = "freq-domain0", "freq-domain1";
225
226        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
227        clock-names = "xo", "alternate";
228
229        #freq-domain-cells = <1>;
230        #clock-cells = <1>;
231      };
232    };
233...
234