1Binding for MediaTek's CPUFreq driver 2===================================== 3 4Required properties: 5- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. 6- clock-names: Should contain the following: 7 "cpu" - The multiplexer for clock input of CPU cluster. 8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock 9 source (usually MAINPLL) when the original CPU PLL is under 10 transition and not stable yet. 11 Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for 12 generic clock consumer properties. 13- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt 14 for detail. 15- proc-supply: Regulator for Vproc of CPU cluster. 16 17Optional properties: 18- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver 19 needs to do "voltage tracking" to step by step scale up/down Vproc and 20 Vsram to fit SoC specific needs. When absent, the voltage scaling 21 flow is handled by hardware, hence no software "voltage tracking" is 22 needed. 23- #cooling-cells: 24- cooling-min-level: 25- cooling-max-level: 26 Please refer to Documentation/devicetree/bindings/thermal/thermal.txt 27 for detail. 28 29Example 1 (MT7623 SoC): 30 31 cpu_opp_table: opp_table { 32 compatible = "operating-points-v2"; 33 opp-shared; 34 35 opp-598000000 { 36 opp-hz = /bits/ 64 <598000000>; 37 opp-microvolt = <1050000>; 38 }; 39 40 opp-747500000 { 41 opp-hz = /bits/ 64 <747500000>; 42 opp-microvolt = <1050000>; 43 }; 44 45 opp-1040000000 { 46 opp-hz = /bits/ 64 <1040000000>; 47 opp-microvolt = <1150000>; 48 }; 49 50 opp-1196000000 { 51 opp-hz = /bits/ 64 <1196000000>; 52 opp-microvolt = <1200000>; 53 }; 54 55 opp-1300000000 { 56 opp-hz = /bits/ 64 <1300000000>; 57 opp-microvolt = <1300000>; 58 }; 59 }; 60 61 cpu0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a7"; 64 reg = <0x0>; 65 clocks = <&infracfg CLK_INFRA_CPUSEL>, 66 <&apmixedsys CLK_APMIXED_MAINPLL>; 67 clock-names = "cpu", "intermediate"; 68 operating-points-v2 = <&cpu_opp_table>; 69 #cooling-cells = <2>; 70 cooling-min-level = <0>; 71 cooling-max-level = <7>; 72 }; 73 cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a7"; 76 reg = <0x1>; 77 operating-points-v2 = <&cpu_opp_table>; 78 }; 79 cpu@2 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a7"; 82 reg = <0x2>; 83 operating-points-v2 = <&cpu_opp_table>; 84 }; 85 cpu@3 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a7"; 88 reg = <0x3>; 89 operating-points-v2 = <&cpu_opp_table>; 90 }; 91 92Example 2 (MT8173 SoC): 93 cpu_opp_table_a: opp_table_a { 94 compatible = "operating-points-v2"; 95 opp-shared; 96 97 opp-507000000 { 98 opp-hz = /bits/ 64 <507000000>; 99 opp-microvolt = <859000>; 100 }; 101 102 opp-702000000 { 103 opp-hz = /bits/ 64 <702000000>; 104 opp-microvolt = <908000>; 105 }; 106 107 opp-1001000000 { 108 opp-hz = /bits/ 64 <1001000000>; 109 opp-microvolt = <983000>; 110 }; 111 112 opp-1105000000 { 113 opp-hz = /bits/ 64 <1105000000>; 114 opp-microvolt = <1009000>; 115 }; 116 117 opp-1183000000 { 118 opp-hz = /bits/ 64 <1183000000>; 119 opp-microvolt = <1028000>; 120 }; 121 122 opp-1404000000 { 123 opp-hz = /bits/ 64 <1404000000>; 124 opp-microvolt = <1083000>; 125 }; 126 127 opp-1508000000 { 128 opp-hz = /bits/ 64 <1508000000>; 129 opp-microvolt = <1109000>; 130 }; 131 132 opp-1573000000 { 133 opp-hz = /bits/ 64 <1573000000>; 134 opp-microvolt = <1125000>; 135 }; 136 }; 137 138 cpu_opp_table_b: opp_table_b { 139 compatible = "operating-points-v2"; 140 opp-shared; 141 142 opp-507000000 { 143 opp-hz = /bits/ 64 <507000000>; 144 opp-microvolt = <828000>; 145 }; 146 147 opp-702000000 { 148 opp-hz = /bits/ 64 <702000000>; 149 opp-microvolt = <867000>; 150 }; 151 152 opp-1001000000 { 153 opp-hz = /bits/ 64 <1001000000>; 154 opp-microvolt = <927000>; 155 }; 156 157 opp-1209000000 { 158 opp-hz = /bits/ 64 <1209000000>; 159 opp-microvolt = <968000>; 160 }; 161 162 opp-1404000000 { 163 opp-hz = /bits/ 64 <1007000000>; 164 opp-microvolt = <1028000>; 165 }; 166 167 opp-1612000000 { 168 opp-hz = /bits/ 64 <1612000000>; 169 opp-microvolt = <1049000>; 170 }; 171 172 opp-1807000000 { 173 opp-hz = /bits/ 64 <1807000000>; 174 opp-microvolt = <1089000>; 175 }; 176 177 opp-1989000000 { 178 opp-hz = /bits/ 64 <1989000000>; 179 opp-microvolt = <1125000>; 180 }; 181 }; 182 183 cpu0: cpu@0 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a53"; 186 reg = <0x000>; 187 enable-method = "psci"; 188 cpu-idle-states = <&CPU_SLEEP_0>; 189 clocks = <&infracfg CLK_INFRA_CA53SEL>, 190 <&apmixedsys CLK_APMIXED_MAINPLL>; 191 clock-names = "cpu", "intermediate"; 192 operating-points-v2 = <&cpu_opp_table_a>; 193 }; 194 195 cpu1: cpu@1 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a53"; 198 reg = <0x001>; 199 enable-method = "psci"; 200 cpu-idle-states = <&CPU_SLEEP_0>; 201 clocks = <&infracfg CLK_INFRA_CA53SEL>, 202 <&apmixedsys CLK_APMIXED_MAINPLL>; 203 clock-names = "cpu", "intermediate"; 204 operating-points-v2 = <&cpu_opp_table_a>; 205 }; 206 207 cpu2: cpu@100 { 208 device_type = "cpu"; 209 compatible = "arm,cortex-a57"; 210 reg = <0x100>; 211 enable-method = "psci"; 212 cpu-idle-states = <&CPU_SLEEP_0>; 213 clocks = <&infracfg CLK_INFRA_CA57SEL>, 214 <&apmixedsys CLK_APMIXED_MAINPLL>; 215 clock-names = "cpu", "intermediate"; 216 operating-points-v2 = <&cpu_opp_table_b>; 217 }; 218 219 cpu3: cpu@101 { 220 device_type = "cpu"; 221 compatible = "arm,cortex-a57"; 222 reg = <0x101>; 223 enable-method = "psci"; 224 cpu-idle-states = <&CPU_SLEEP_0>; 225 clocks = <&infracfg CLK_INFRA_CA57SEL>, 226 <&apmixedsys CLK_APMIXED_MAINPLL>; 227 clock-names = "cpu", "intermediate"; 228 operating-points-v2 = <&cpu_opp_table_b>; 229 }; 230 231 &cpu0 { 232 proc-supply = <&mt6397_vpca15_reg>; 233 }; 234 235 &cpu1 { 236 proc-supply = <&mt6397_vpca15_reg>; 237 }; 238 239 &cpu2 { 240 proc-supply = <&da9211_vcpu_reg>; 241 sram-supply = <&mt6397_vsramca7_reg>; 242 }; 243 244 &cpu3 { 245 proc-supply = <&da9211_vcpu_reg>; 246 sram-supply = <&mt6397_vsramca7_reg>; 247 }; 248