1Device Tree Clock bindings for the Zynq 7000 EPP
2
3The Zynq EPP has several different clk providers, each with there own bindings.
4The purpose of this document is to document their usage.
5
6See clock_bindings.txt for more information on the generic clock bindings.
7See Chapter 25 of Zynq TRM for more information about Zynq clocks.
8
9== PLLs ==
10
11Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
12
13Required properties:
14- #clock-cells : shall be 0 (only one clock is output from this node)
15- compatible : "xlnx,zynq-pll"
16- reg : pair of u32 values, which are the address offsets within the SLCR
17        of the relevant PLL_CTRL register and PLL_CFG register respectively
18- clocks : phandle for parent clock.  should be the phandle for ps_clk
19
20Optional properties:
21- clock-output-names : name of the output clock
22
23Example:
24	armpll: armpll {
25		#clock-cells = <0>;
26		compatible = "xlnx,zynq-pll";
27		clocks = <&ps_clk>;
28		reg = <0x100 0x110>;
29		clock-output-names = "armpll";
30	};
31
32== Peripheral clocks ==
33
34Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
35
36Required properties:
37- #clock-cells : shall be 1
38- compatible : "xlnx,zynq-periph-clock"
39- reg : a single u32 value, describing the offset within the SLCR where
40        the CLK_CTRL register is found for this peripheral
41- clocks : phandle for parent clocks.  should hold phandles for
42           the IO_PLL, ARM_PLL, and DDR_PLL in order
43- clock-output-names : names of the output clock(s).  For peripherals that have
44                       two output clocks (for example, the UART), two clocks
45                       should be listed.
46
47Example:
48	uart_clk: uart_clk {
49		#clock-cells = <1>;
50		compatible = "xlnx,zynq-periph-clock";
51		clocks = <&iopll &armpll &ddrpll>;
52		reg = <0x154>;
53		clock-output-names = "uart0_ref_clk",
54				     "uart1_ref_clk";
55	};
56