1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx Versal clock controller
8
9maintainers:
10  - Michal Simek <michal.simek@amd.com>
11
12description: |
13  The clock controller is a hardware block of Xilinx versal clock tree. It
14  reads required input clock frequencies from the devicetree and acts as clock
15  provider for all clock consumers of PS clocks.
16
17select: false
18
19properties:
20  compatible:
21    const: xlnx,versal-clk
22
23  "#clock-cells":
24    const: 1
25
26  clocks:
27    description: List of clock specifiers which are external input
28      clocks to the given clock controller.
29    items:
30      - description: reference clock
31      - description: alternate reference clock
32      - description: alternate reference clock for programmable logic
33
34  clock-names:
35    items:
36      - const: ref
37      - const: alt_ref
38      - const: pl_alt_ref
39
40required:
41  - compatible
42  - "#clock-cells"
43  - clocks
44  - clock-names
45
46additionalProperties: false
47
48examples:
49  - |
50    firmware {
51      zynqmp_firmware: zynqmp-firmware {
52        compatible = "xlnx,zynqmp-firmware";
53        method = "smc";
54        versal_clk: clock-controller {
55          #clock-cells = <1>;
56          compatible = "xlnx,versal-clk";
57          clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
58          clock-names = "ref", "alt_ref", "pl_alt_ref";
59        };
60      };
61    };
62...
63