1Device Tree Clock bindings for APM X-Gene
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9	"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10	"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11	"apm,xgene-device-clock" - for a X-Gene device clock
12	"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
13	"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
14
15Required properties for SoC or PCP PLL clocks:
16- reg : shall be the physical PLL register address for the pll clock.
17- clocks : shall be the input parent clock phandle for the clock. This should
18	be the reference clock.
19- #clock-cells : shall be set to 1.
20- clock-output-names : shall be the name of the PLL referenced by derive
21  clock.
22Optional properties for PLL clocks:
23- clock-names : shall be the name of the PLL. If missing, use the device name.
24
25Required properties for device clocks:
26- reg : shall be a list of address and length pairs describing the CSR
27         reset and/or the divider. Either may be omitted, but at least
28         one must be present.
29 - reg-names : shall be a string list describing the reg resource. This
30               may include "csr-reg" and/or "div-reg". If this property
31               is not present, the reg property is assumed to describe
32               only "csr-reg".
33- clocks : shall be the input parent clock phandle for the clock.
34- #clock-cells : shall be set to 1.
35- clock-output-names : shall be the name of the device referenced.
36Optional properties for device clocks:
37- clock-names : shall be the name of the device clock. If missing, use the
38                device name.
39- csr-offset : Offset to the CSR reset register from the reset address base.
40               Default is 0.
41- csr-mask : CSR reset mask bit. Default is 0xF.
42- enable-offset : Offset to the enable register from the reset address base.
43                  Default is 0x8.
44- enable-mask : CSR enable mask bit. Default is 0xF.
45- divider-offset : Offset to the divider CSR register from the divider base.
46                   Default is 0x0.
47- divider-width : Width of the divider register. Default is 0.
48- divider-shift : Bit shift of the divider register. Default is 0.
49
50For example:
51
52	pcppll: pcppll@17000100 {
53		compatible = "apm,xgene-pcppll-clock";
54		#clock-cells = <1>;
55		clocks = <&refclk 0>;
56		clock-names = "pcppll";
57		reg = <0x0 0x17000100 0x0 0x1000>;
58		clock-output-names = "pcppll";
59		type = <0>;
60	};
61
62	socpll: socpll@17000120 {
63		compatible = "apm,xgene-socpll-clock";
64		#clock-cells = <1>;
65		clocks = <&refclk 0>;
66		clock-names = "socpll";
67		reg = <0x0 0x17000120 0x0 0x1000>;
68		clock-output-names = "socpll";
69		type = <1>;
70	};
71
72	qmlclk: qmlclk {
73		compatible = "apm,xgene-device-clock";
74		#clock-cells = <1>;
75		clocks = <&socplldiv2 0>;
76		clock-names = "qmlclk";
77		reg = <0x0 0x1703C000 0x0 0x1000>;
78		reg-name = "csr-reg";
79		clock-output-names = "qmlclk";
80	};
81
82	ethclk: ethclk {
83		compatible = "apm,xgene-device-clock";
84		#clock-cells = <1>;
85		clocks = <&socplldiv2 0>;
86		clock-names = "ethclk";
87		reg = <0x0 0x17000000 0x0 0x1000>;
88		reg-names = "div-reg";
89		divider-offset = <0x238>;
90		divider-width = <0x9>;
91		divider-shift = <0x0>;
92		clock-output-names = "ethclk";
93	};
94
95	apbclk: apbclk {
96		compatible = "apm,xgene-device-clock";
97		#clock-cells = <1>;
98		clocks = <&ahbclk 0>;
99		clock-names = "apbclk";
100		reg = <0x0 0x1F2AC000 0x0 0x1000
101			0x0 0x1F2AC000 0x0 0x1000>;
102		reg-names = "csr-reg", "div-reg";
103		csr-offset = <0x0>;
104		csr-mask = <0x200>;
105		enable-offset = <0x8>;
106		enable-mask = <0x200>;
107		divider-offset = <0x10>;
108		divider-width = <0x2>;
109		divider-shift = <0x0>;
110		flags = <0x8>;
111		clock-output-names = "apbclk";
112	};
113
114