1938cc3a1SLoc HoDevice Tree Clock bindings for APM X-Gene 2938cc3a1SLoc Ho 3938cc3a1SLoc HoThis binding uses the common clock binding[1]. 4938cc3a1SLoc Ho 5938cc3a1SLoc Ho[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6938cc3a1SLoc Ho 7938cc3a1SLoc HoRequired properties: 8938cc3a1SLoc Ho- compatible : shall be one of the following: 9938cc3a1SLoc Ho "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock 10938cc3a1SLoc Ho "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock 11938cc3a1SLoc Ho "apm,xgene-device-clock" - for a X-Gene device clock 12938cc3a1SLoc Ho 13938cc3a1SLoc HoRequired properties for SoC or PCP PLL clocks: 14938cc3a1SLoc Ho- reg : shall be the physical PLL register address for the pll clock. 15938cc3a1SLoc Ho- clocks : shall be the input parent clock phandle for the clock. This should 16938cc3a1SLoc Ho be the reference clock. 17938cc3a1SLoc Ho- #clock-cells : shall be set to 1. 18938cc3a1SLoc Ho- clock-output-names : shall be the name of the PLL referenced by derive 19938cc3a1SLoc Ho clock. 20938cc3a1SLoc HoOptional properties for PLL clocks: 21938cc3a1SLoc Ho- clock-names : shall be the name of the PLL. If missing, use the device name. 22938cc3a1SLoc Ho 23938cc3a1SLoc HoRequired properties for device clocks: 24938cc3a1SLoc Ho- reg : shall be a list of address and length pairs describing the CSR 25938cc3a1SLoc Ho reset and/or the divider. Either may be omitted, but at least 26938cc3a1SLoc Ho one must be present. 27938cc3a1SLoc Ho - reg-names : shall be a string list describing the reg resource. This 28938cc3a1SLoc Ho may include "csr-reg" and/or "div-reg". If this property 29938cc3a1SLoc Ho is not present, the reg property is assumed to describe 30938cc3a1SLoc Ho only "csr-reg". 31938cc3a1SLoc Ho- clocks : shall be the input parent clock phandle for the clock. 32938cc3a1SLoc Ho- #clock-cells : shall be set to 1. 33938cc3a1SLoc Ho- clock-output-names : shall be the name of the device referenced. 34938cc3a1SLoc HoOptional properties for device clocks: 35938cc3a1SLoc Ho- clock-names : shall be the name of the device clock. If missing, use the 36938cc3a1SLoc Ho device name. 37938cc3a1SLoc Ho- csr-offset : Offset to the CSR reset register from the reset address base. 38938cc3a1SLoc Ho Default is 0. 39938cc3a1SLoc Ho- csr-mask : CSR reset mask bit. Default is 0xF. 40938cc3a1SLoc Ho- enable-offset : Offset to the enable register from the reset address base. 41938cc3a1SLoc Ho Default is 0x8. 42938cc3a1SLoc Ho- enable-mask : CSR enable mask bit. Default is 0xF. 43938cc3a1SLoc Ho- divider-offset : Offset to the divider CSR register from the divider base. 44938cc3a1SLoc Ho Default is 0x0. 45938cc3a1SLoc Ho- divider-width : Width of the divider register. Default is 0. 46938cc3a1SLoc Ho- divider-shift : Bit shift of the divider register. Default is 0. 47938cc3a1SLoc Ho 48938cc3a1SLoc HoFor example: 49938cc3a1SLoc Ho 50938cc3a1SLoc Ho pcppll: pcppll@17000100 { 51938cc3a1SLoc Ho compatible = "apm,xgene-pcppll-clock"; 52938cc3a1SLoc Ho #clock-cells = <1>; 53938cc3a1SLoc Ho clocks = <&refclk 0>; 54938cc3a1SLoc Ho clock-names = "pcppll"; 55938cc3a1SLoc Ho reg = <0x0 0x17000100 0x0 0x1000>; 56938cc3a1SLoc Ho clock-output-names = "pcppll"; 57938cc3a1SLoc Ho type = <0>; 58938cc3a1SLoc Ho }; 59938cc3a1SLoc Ho 60938cc3a1SLoc Ho socpll: socpll@17000120 { 61938cc3a1SLoc Ho compatible = "apm,xgene-socpll-clock"; 62938cc3a1SLoc Ho #clock-cells = <1>; 63938cc3a1SLoc Ho clocks = <&refclk 0>; 64938cc3a1SLoc Ho clock-names = "socpll"; 65938cc3a1SLoc Ho reg = <0x0 0x17000120 0x0 0x1000>; 66938cc3a1SLoc Ho clock-output-names = "socpll"; 67938cc3a1SLoc Ho type = <1>; 68938cc3a1SLoc Ho }; 69938cc3a1SLoc Ho 70938cc3a1SLoc Ho qmlclk: qmlclk { 71938cc3a1SLoc Ho compatible = "apm,xgene-device-clock"; 72938cc3a1SLoc Ho #clock-cells = <1>; 73938cc3a1SLoc Ho clocks = <&socplldiv2 0>; 74938cc3a1SLoc Ho clock-names = "qmlclk"; 75938cc3a1SLoc Ho reg = <0x0 0x1703C000 0x0 0x1000>; 76938cc3a1SLoc Ho reg-name = "csr-reg"; 77938cc3a1SLoc Ho clock-output-names = "qmlclk"; 78938cc3a1SLoc Ho }; 79938cc3a1SLoc Ho 80938cc3a1SLoc Ho ethclk: ethclk { 81938cc3a1SLoc Ho compatible = "apm,xgene-device-clock"; 82938cc3a1SLoc Ho #clock-cells = <1>; 83938cc3a1SLoc Ho clocks = <&socplldiv2 0>; 84938cc3a1SLoc Ho clock-names = "ethclk"; 85938cc3a1SLoc Ho reg = <0x0 0x17000000 0x0 0x1000>; 86938cc3a1SLoc Ho reg-names = "div-reg"; 87938cc3a1SLoc Ho divider-offset = <0x238>; 88938cc3a1SLoc Ho divider-width = <0x9>; 89938cc3a1SLoc Ho divider-shift = <0x0>; 90938cc3a1SLoc Ho clock-output-names = "ethclk"; 91938cc3a1SLoc Ho }; 92938cc3a1SLoc Ho 93938cc3a1SLoc Ho apbclk: apbclk { 94938cc3a1SLoc Ho compatible = "apm,xgene-device-clock"; 95938cc3a1SLoc Ho #clock-cells = <1>; 96938cc3a1SLoc Ho clocks = <&ahbclk 0>; 97938cc3a1SLoc Ho clock-names = "apbclk"; 98938cc3a1SLoc Ho reg = <0x0 0x1F2AC000 0x0 0x1000 99938cc3a1SLoc Ho 0x0 0x1F2AC000 0x0 0x1000>; 100938cc3a1SLoc Ho reg-names = "csr-reg", "div-reg"; 101938cc3a1SLoc Ho csr-offset = <0x0>; 102938cc3a1SLoc Ho csr-mask = <0x200>; 103938cc3a1SLoc Ho enable-offset = <0x8>; 104938cc3a1SLoc Ho enable-mask = <0x200>; 105938cc3a1SLoc Ho divider-offset = <0x10>; 106938cc3a1SLoc Ho divider-width = <0x2>; 107938cc3a1SLoc Ho divider-shift = <0x0>; 108938cc3a1SLoc Ho flags = <0x8>; 109938cc3a1SLoc Ho clock-output-names = "apbclk"; 110938cc3a1SLoc Ho }; 111938cc3a1SLoc Ho 112