1Binding for TI mux clock.
2
3Binding status: Unstable - ABI compatibility may be broken in the future
4
5This binding uses the common clock binding[1].  It assumes a
6register-mapped multiplexer with multiple input clock signals or
7parents, one of which can be selected as output.  This clock does not
8gate or adjust the parent rate via a divider or multiplier.
9
10By default the "clocks" property lists the parents in the same order
11as they are programmed into the regster.  E.g:
12
13	clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
14
15results in programming the register as follows:
16
17register value		selected parent clock
180			foo_clock
191			bar_clock
202			baz_clock
21
22Some clock controller IPs do not allow a value of zero to be programmed
23into the register, instead indexing begins at 1.  The optional property
24"index-starts-at-one" modified the scheme as follows:
25
26register value		selected clock parent
271			foo_clock
282			bar_clock
293			baz_clock
30
31The binding must provide the register to control the mux. Optionally
32the number of bits to shift the control field in the register can be
33supplied. If the shift value is missing it is the same as supplying
34a zero shift.
35
36[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37
38Required properties:
39- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
40- #clock-cells : from common clock binding; shall be set to 0.
41- clocks : link phandles of parent clocks
42- reg : register offset for register controlling adjustable mux
43
44Optional properties:
45- ti,bit-shift : number of bits to shift the bit-mask, defaults to
46  0 if not present
47- ti,index-starts-at-one : valid input select programming starts at 1, not
48  zero
49- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
50  not supported by the composite-mux-clock subtype
51
52Examples:
53
54sys_clkin_ck: sys_clkin_ck@4a306110 {
55	#clock-cells = <0>;
56	compatible = "ti,mux-clock";
57	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
58	reg = <0x0110>;
59	ti,index-starts-at-one;
60};
61
62abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
63	#clock-cells = <0>;
64	compatible = "ti,mux-clock";
65	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
66	ti,bit-shift = <24>;
67	reg = <0x0108>;
68};
69
70mcbsp5_mux_fck: mcbsp5_mux_fck {
71	#clock-cells = <0>;
72	compatible = "ti,composite-mux-clock";
73	clocks = <&core_96m_fck>, <&mcbsp_clks>;
74	ti,bit-shift = <4>;
75	reg = <0x02d8>;
76};
77