1Binding for Texas Instruments DPLL clock. 2 3Binding status: Unstable - ABI compatibility may be broken in the future 4 5This binding uses the common clock binding[1]. It assumes a 6register-mapped DPLL with usually two selectable input clocks 7(reference clock and bypass clock), with digital phase locked 8loop logic for multiplying the input clock to a desired output 9clock. This clock also typically supports different operation 10modes (locked, low power stop etc.) This binding has several 11sub-types, which effectively result in slightly different setup 12for the actual DPLL clock. 13 14[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 15 16Required properties: 17- compatible : shall be one of: 18 "ti,omap3-dpll-clock", 19 "ti,omap3-dpll-core-clock", 20 "ti,omap3-dpll-per-clock", 21 "ti,omap3-dpll-per-j-type-clock", 22 "ti,omap4-dpll-clock", 23 "ti,omap4-dpll-x2-clock", 24 "ti,omap4-dpll-core-clock", 25 "ti,omap4-dpll-m4xen-clock", 26 "ti,omap4-dpll-j-type-clock", 27 "ti,am3-dpll-no-gate-clock", 28 "ti,am3-dpll-j-type-clock", 29 "ti,am3-dpll-no-gate-j-type-clock", 30 "ti,am3-dpll-clock", 31 "ti,am3-dpll-core-clock", 32 "ti,am3-dpll-x2-clock", 33 34- #clock-cells : from common clock binding; shall be set to 0. 35- clocks : link phandles of parent clocks, first entry lists reference clock 36 and second entry bypass clock 37- reg : offsets for the register set for controlling the DPLL. 38 Registers are listed in following order: 39 "control" - contains the control register base address 40 "idlest" - contains the idle status register base address 41 "mult-div1" - contains the multiplier / divider register base address 42 "autoidle" - contains the autoidle register base address (optional) 43 ti,am3-* dpll types do not have autoidle register 44 45Optional properties: 46- DPLL mode setting - defining any one or more of the following overrides 47 default setting. 48 - ti,low-power-stop : DPLL supports low power stop mode, gating output 49 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock 50 - ti,lock : DPLL locks in programmed rate 51 52Examples: 53 dpll_core_ck: dpll_core_ck@44e00490 { 54 #clock-cells = <0>; 55 compatible = "ti,omap4-dpll-core-clock"; 56 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 57 reg = <0x490>, <0x45c>, <0x488>, <0x468>; 58 }; 59 60 dpll2_ck: dpll2_ck@48004004 { 61 #clock-cells = <0>; 62 compatible = "ti,omap3-dpll-clock"; 63 clocks = <&sys_ck>, <&dpll2_fck>; 64 ti,low-power-stop; 65 ti,low-power-bypass; 66 ti,lock; 67 reg = <0x4>, <0x24>, <0x34>, <0x40>; 68 }; 69 70 dpll_core_ck: dpll_core_ck@44e00490 { 71 #clock-cells = <0>; 72 compatible = "ti,am3-dpll-core-clock"; 73 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 74 reg = <0x90>, <0x5c>, <0x68>; 75 }; 76