1Binding for Texas Instruments APLL clock.
2
3Binding status: Unstable - ABI compatibility may be broken in the future
4
5This binding uses the common clock binding[1].  It assumes a
6register-mapped APLL with usually two selectable input clocks
7(reference clock and bypass clock), with analog phase locked
8loop logic for multiplying the input clock to a desired output
9clock. This clock also typically supports different operation
10modes (locked, low power stop etc.) APLL mostly behaves like
11a subtype of a DPLL [2], although a simplified one at that.
12
13[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
15
16Required properties:
17- compatible : shall be "ti,dra7-apll-clock"
18- #clock-cells : from common clock binding; shall be set to 0.
19- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20- reg : address and length of the register set for controlling the APLL.
21  It contains the information of registers in the following order:
22	"control" - contains the control register base address
23	"idlest" - contains the idlest register base address
24
25Examples:
26	apll_pcie_ck: apll_pcie_ck@4a008200 {
27		#clock-cells = <0>;
28		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
29		reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
30		compatible = "ti,dra7-apll-clock";
31	};
32