1*f2b883bbSLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f2b883bbSLinus Walleij%YAML 1.2 3*f2b883bbSLinus Walleij--- 4*f2b883bbSLinus Walleij$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# 5*f2b883bbSLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f2b883bbSLinus Walleij 7*f2b883bbSLinus Walleijtitle: ST-Ericsson DB8500 (U8500) clocks 8*f2b883bbSLinus Walleij 9*f2b883bbSLinus Walleijmaintainers: 10*f2b883bbSLinus Walleij - Ulf Hansson <ulf.hansson@linaro.org> 11*f2b883bbSLinus Walleij - Linus Walleij <linus.walleij@linaro.org> 12*f2b883bbSLinus Walleij 13*f2b883bbSLinus Walleijdescription: While named "U8500 clocks" these clocks are inside the 14*f2b883bbSLinus Walleij DB8500 digital baseband system-on-chip and its siblings such as 15*f2b883bbSLinus Walleij DB8520. These bindings consider the clocks present in the SoC 16*f2b883bbSLinus Walleij itself, not off-chip clocks. There are four different on-chip 17*f2b883bbSLinus Walleij clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and 18*f2b883bbSLinus Walleij control management unit) clocks and PRCC (peripheral reset and 19*f2b883bbSLinus Walleij clock controller) clocks. For some reason PRCC 4 does not exist so 20*f2b883bbSLinus Walleij the itemization can be a bit unintuitive. 21*f2b883bbSLinus Walleij 22*f2b883bbSLinus Walleijproperties: 23*f2b883bbSLinus Walleij compatible: 24*f2b883bbSLinus Walleij enum: 25*f2b883bbSLinus Walleij - stericsson,u8500-clks 26*f2b883bbSLinus Walleij - stericsson,u8540-clks 27*f2b883bbSLinus Walleij - stericsson,u9540-clks 28*f2b883bbSLinus Walleij 29*f2b883bbSLinus Walleij reg: 30*f2b883bbSLinus Walleij items: 31*f2b883bbSLinus Walleij - description: PRCC 1 register area 32*f2b883bbSLinus Walleij - description: PRCC 2 register area 33*f2b883bbSLinus Walleij - description: PRCC 3 register area 34*f2b883bbSLinus Walleij - description: PRCC 5 register area 35*f2b883bbSLinus Walleij - description: PRCC 6 register area 36*f2b883bbSLinus Walleij 37*f2b883bbSLinus Walleij prcmu-clock: 38*f2b883bbSLinus Walleij description: A subnode with one clock cell for PRCMU (power, reset, control 39*f2b883bbSLinus Walleij management unit) clocks. The cell indicates which PRCMU clock in the 40*f2b883bbSLinus Walleij prcmu-clock node the consumer wants to use. 41*f2b883bbSLinus Walleij type: object 42*f2b883bbSLinus Walleij 43*f2b883bbSLinus Walleij properties: 44*f2b883bbSLinus Walleij '#clock-cells': 45*f2b883bbSLinus Walleij const: 1 46*f2b883bbSLinus Walleij 47*f2b883bbSLinus Walleij additionalProperties: false 48*f2b883bbSLinus Walleij 49*f2b883bbSLinus Walleij prcc-periph-clock: 50*f2b883bbSLinus Walleij description: A subnode with two clock cells for PRCC (peripheral 51*f2b883bbSLinus Walleij reset and clock controller) peripheral clocks. The first cell indicates 52*f2b883bbSLinus Walleij which PRCC block the consumer wants to use, possible values are 1, 2, 3, 53*f2b883bbSLinus Walleij 5, 6. The second cell indicates which clock inside the PRCC block it 54*f2b883bbSLinus Walleij wants, possible values are 0 thru 31. 55*f2b883bbSLinus Walleij type: object 56*f2b883bbSLinus Walleij 57*f2b883bbSLinus Walleij properties: 58*f2b883bbSLinus Walleij '#clock-cells': 59*f2b883bbSLinus Walleij const: 2 60*f2b883bbSLinus Walleij 61*f2b883bbSLinus Walleij additionalProperties: false 62*f2b883bbSLinus Walleij 63*f2b883bbSLinus Walleij prcc-kernel-clock: 64*f2b883bbSLinus Walleij description: A subnode with two clock cells for PRCC (peripheral reset 65*f2b883bbSLinus Walleij and clock controller) kernel clocks. The first cell indicates which PRCC 66*f2b883bbSLinus Walleij block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The 67*f2b883bbSLinus Walleij second cell indicates which clock inside the PRCC block it wants, possible 68*f2b883bbSLinus Walleij values are 0 thru 31. 69*f2b883bbSLinus Walleij type: object 70*f2b883bbSLinus Walleij 71*f2b883bbSLinus Walleij properties: 72*f2b883bbSLinus Walleij '#clock-cells': 73*f2b883bbSLinus Walleij const: 2 74*f2b883bbSLinus Walleij 75*f2b883bbSLinus Walleij additionalProperties: false 76*f2b883bbSLinus Walleij 77*f2b883bbSLinus Walleij prcc-reset-controller: 78*f2b883bbSLinus Walleij description: A subnode with two reset cells for the reset portions of the 79*f2b883bbSLinus Walleij PRCC (peripheral reset and clock controller). The first cell indicates 80*f2b883bbSLinus Walleij which PRCC block the consumer wants to use, possible values are 1, 2, 3 81*f2b883bbSLinus Walleij 5 and 6. The second cell indicates which reset line inside the PRCC block 82*f2b883bbSLinus Walleij it wants to control, possible values are 0 thru 31. 83*f2b883bbSLinus Walleij type: object 84*f2b883bbSLinus Walleij 85*f2b883bbSLinus Walleij properties: 86*f2b883bbSLinus Walleij '#reset-cells': 87*f2b883bbSLinus Walleij const: 2 88*f2b883bbSLinus Walleij 89*f2b883bbSLinus Walleij additionalProperties: false 90*f2b883bbSLinus Walleij 91*f2b883bbSLinus Walleij rtc32k-clock: 92*f2b883bbSLinus Walleij description: A subnode with zero clock cells for the 32kHz RTC clock. 93*f2b883bbSLinus Walleij type: object 94*f2b883bbSLinus Walleij 95*f2b883bbSLinus Walleij properties: 96*f2b883bbSLinus Walleij '#clock-cells': 97*f2b883bbSLinus Walleij const: 0 98*f2b883bbSLinus Walleij 99*f2b883bbSLinus Walleij additionalProperties: false 100*f2b883bbSLinus Walleij 101*f2b883bbSLinus Walleij smp-twd-clock: 102*f2b883bbSLinus Walleij description: A subnode for the ARM SMP Timer Watchdog cluster with zero 103*f2b883bbSLinus Walleij clock cells. 104*f2b883bbSLinus Walleij type: object 105*f2b883bbSLinus Walleij 106*f2b883bbSLinus Walleij properties: 107*f2b883bbSLinus Walleij '#clock-cells': 108*f2b883bbSLinus Walleij const: 0 109*f2b883bbSLinus Walleij 110*f2b883bbSLinus Walleij additionalProperties: false 111*f2b883bbSLinus Walleij 112*f2b883bbSLinus Walleijrequired: 113*f2b883bbSLinus Walleij - compatible 114*f2b883bbSLinus Walleij - reg 115*f2b883bbSLinus Walleij - prcmu-clock 116*f2b883bbSLinus Walleij - prcc-periph-clock 117*f2b883bbSLinus Walleij - prcc-kernel-clock 118*f2b883bbSLinus Walleij - rtc32k-clock 119*f2b883bbSLinus Walleij - smp-twd-clock 120*f2b883bbSLinus Walleij 121*f2b883bbSLinus WalleijadditionalProperties: false 122