1Binding for a type of quad channel digital frequency synthesizer found on
2certain STMicroelectronics consumer electronics SoC devices.
3
4This version contains a programmable PLL which can generate up to 216, 432
5or 660MHz (from a 30MHz oscillator input) as the input to the digital
6synthesizers.
7
8This binding uses the common clock binding[1].
9
10[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11
12Required properties:
13- compatible : shall be:
14  "st,stih416-quadfs216",	"st,quadfs"
15  "st,stih416-quadfs432",	"st,quadfs"
16  "st,stih416-quadfs660-E",	"st,quadfs"
17  "st,stih416-quadfs660-F",	"st,quadfs"
18
19- #clock-cells : from common clock binding; shall be set to 1.
20
21- reg : A Base address and length of the register set.
22
23- clocks : from common clock binding
24
25- clock-output-names : From common clock binding. The block has 4
26                       clock outputs but not all of them in a specific instance
27                       have to be used in the SoC. If a clock name is left as
28                       an empty string then no clock will be created for the
29                       output associated with that string index. If fewer than
30                       4 strings are provided then no clocks will be created
31                       for the remaining outputs.
32
33Example:
34
35	CLOCKGEN_E: CLOCKGEN_E {
36                #clock-cells = <1>;
37                compatible = "st,stih416-quadfs660-E", "st,quadfs";
38                reg = <0xfd3208bc 0xB0>;
39
40                clocks = <&CLK_SYSIN>;
41                clock-output-names = "CLK_M_PIX_MDTP_0",
42                                        "CLK_M_PIX_MDTP_1",
43                                        "CLK_M_PIX_MDTP_2",
44                                        "CLK_M_MPELPC";
45        };
46