1Binding for a ST pll clock driver.
2
3This binding uses the common clock binding[1].
4Base address is located to the parent node. See clock binding[2]
5
6[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
8
9Required properties:
10
11- compatible : shall be:
12	"st,clkgena-prediv-c65",	"st,clkgena-prediv"
13	"st,clkgena-prediv-c32",	"st,clkgena-prediv"
14
15	"st,clkgena-plls-c65"
16	"st,plls-c32-a1x-0",		"st,clkgen-plls-c32"
17	"st,plls-c32-a1x-1",		"st,clkgen-plls-c32"
18	"st,stih415-plls-c32-a9",	"st,clkgen-plls-c32"
19	"st,stih415-plls-c32-ddr",	"st,clkgen-plls-c32"
20	"st,stih416-plls-c32-a9",	"st,clkgen-plls-c32"
21	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"
22
23	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"
24	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"
25
26
27- #clock-cells : From common clock binding; shall be set to 1.
28
29- clocks : From common clock binding
30
31- clock-output-names : From common clock binding.
32
33Example:
34
35	clockgenA@fee62000 {
36		reg = <0xfee62000 0xb48>;
37
38		CLK_S_A0_PLL: CLK_S_A0_PLL {
39			#clock-cells = <1>;
40			compatible = "st,clkgena-plls-c65";
41
42			clocks = <&CLK_SYSIN>;
43
44			clock-output-names = "CLK_S_A0_PLL0_HS",
45					     "CLK_S_A0_PLL0_LS",
46					     "CLK_S_A0_PLL1";
47		};
48	};
49