1Binding for a Clockgen hardware block found on 2certain STMicroelectronics consumer electronics SoC devices. 3 4A Clockgen node can contain pll, diviser or multiplexer nodes. 5 6We will find only the base address of the Clockgen, this base 7address is common of all subnode. 8 9 clockgen_node { 10 reg = <>; 11 12 pll_node { 13 ... 14 }; 15 16 prediv_node { 17 ... 18 }; 19 20 divmux_node { 21 ... 22 }; 23 24 quadfs_node { 25 ... 26 }; 27 28 mux_node { 29 ... 30 }; 31 32 vcc_node { 33 ... 34 }; 35 ... 36 }; 37 38This binding uses the common clock binding[1]. 39Each subnode should use the binding discribe in [2]..[7] 40 41[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 42[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt 43[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt 44[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt 45[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt 46[6] Documentation/devicetree/bindings/clock/st,vcc.txt 47[7] Documentation/devicetree/bindings/clock/st,quadfs.txt 48 49 50Required properties: 51- reg : A Base address and length of the register set. 52 53Example: 54 55 clockgen-a@fee62000 { 56 57 reg = <0xfee62000 0xb48>; 58 59 clk_s_a0_pll: clk-s-a0-pll { 60 #clock-cells = <1>; 61 compatible = "st,clkgena-plls-c65"; 62 63 clocks = <&clk-sysin>; 64 65 clock-output-names = "clk-s-a0-pll0-hs", 66 "clk-s-a0-pll0-ls", 67 "clk-s-a0-pll1"; 68 }; 69 70 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { 71 #clock-cells = <0>; 72 compatible = "st,clkgena-prediv-c65", 73 "st,clkgena-prediv"; 74 75 clocks = <&clk_sysin>; 76 77 clock-output-names = "clk-s-a0-osc-prediv"; 78 }; 79 80 clk_s_a0_hs: clk-s-a0-hs { 81 #clock-cells = <1>; 82 compatible = "st,clkgena-divmux-c65-hs", 83 "st,clkgena-divmux"; 84 85 clocks = <&clk-s_a0_osc_prediv>, 86 <&clk-s_a0_pll 0>, /* pll0 hs */ 87 <&clk-s_a0_pll 2>; /* pll1 */ 88 89 clock-output-names = "clk-s-fdma-0", 90 "clk-s-fdma-1", 91 ""; /* clk-s-jit-sense */ 92 /* fourth output unused */ 93 }; 94 }; 95 96