1be10afcdSGabriel FERNANDEZBinding for a Clockgen hardware block found on 2be10afcdSGabriel FERNANDEZcertain STMicroelectronics consumer electronics SoC devices. 3be10afcdSGabriel FERNANDEZ 4be10afcdSGabriel FERNANDEZA Clockgen node can contain pll, diviser or multiplexer nodes. 5be10afcdSGabriel FERNANDEZ 6be10afcdSGabriel FERNANDEZWe will find only the base address of the Clockgen, this base 7be10afcdSGabriel FERNANDEZaddress is common of all subnode. 8be10afcdSGabriel FERNANDEZ 9be10afcdSGabriel FERNANDEZ clockgen_node { 10be10afcdSGabriel FERNANDEZ reg = <>; 11be10afcdSGabriel FERNANDEZ 12be10afcdSGabriel FERNANDEZ pll_node { 13be10afcdSGabriel FERNANDEZ ... 14be10afcdSGabriel FERNANDEZ }; 15be10afcdSGabriel FERNANDEZ 16be10afcdSGabriel FERNANDEZ prediv_node { 17be10afcdSGabriel FERNANDEZ ... 18be10afcdSGabriel FERNANDEZ }; 19be10afcdSGabriel FERNANDEZ 20be10afcdSGabriel FERNANDEZ divmux_node { 21be10afcdSGabriel FERNANDEZ ... 22be10afcdSGabriel FERNANDEZ }; 23be10afcdSGabriel FERNANDEZ 24be10afcdSGabriel FERNANDEZ quadfs_node { 25be10afcdSGabriel FERNANDEZ ... 26be10afcdSGabriel FERNANDEZ }; 270268099cSGabriel FERNANDEZ 280268099cSGabriel FERNANDEZ mux_node { 290268099cSGabriel FERNANDEZ ... 300268099cSGabriel FERNANDEZ }; 310268099cSGabriel FERNANDEZ 320268099cSGabriel FERNANDEZ vcc_node { 330268099cSGabriel FERNANDEZ ... 340268099cSGabriel FERNANDEZ }; 353414666dSGabriel FERNANDEZ 363414666dSGabriel FERNANDEZ flexgen_node { 373414666dSGabriel FERNANDEZ ... 383414666dSGabriel FERNANDEZ }; 39be10afcdSGabriel FERNANDEZ ... 40be10afcdSGabriel FERNANDEZ }; 41be10afcdSGabriel FERNANDEZ 42be10afcdSGabriel FERNANDEZThis binding uses the common clock binding[1]. 430268099cSGabriel FERNANDEZEach subnode should use the binding discribe in [2]..[7] 44be10afcdSGabriel FERNANDEZ 45be10afcdSGabriel FERNANDEZ[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 460268099cSGabriel FERNANDEZ[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt 470268099cSGabriel FERNANDEZ[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt 480268099cSGabriel FERNANDEZ[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt 490268099cSGabriel FERNANDEZ[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt 500268099cSGabriel FERNANDEZ[6] Documentation/devicetree/bindings/clock/st,vcc.txt 510268099cSGabriel FERNANDEZ[7] Documentation/devicetree/bindings/clock/st,quadfs.txt 523414666dSGabriel FERNANDEZ[8] Documentation/devicetree/bindings/clock/st,flexgen.txt 530268099cSGabriel FERNANDEZ 54be10afcdSGabriel FERNANDEZ 55be10afcdSGabriel FERNANDEZRequired properties: 56be10afcdSGabriel FERNANDEZ- reg : A Base address and length of the register set. 57be10afcdSGabriel FERNANDEZ 58be10afcdSGabriel FERNANDEZExample: 59be10afcdSGabriel FERNANDEZ 600268099cSGabriel FERNANDEZ clockgen-a@fee62000 { 61be10afcdSGabriel FERNANDEZ 62be10afcdSGabriel FERNANDEZ reg = <0xfee62000 0xb48>; 63be10afcdSGabriel FERNANDEZ 640268099cSGabriel FERNANDEZ clk_s_a0_pll: clk-s-a0-pll { 65be10afcdSGabriel FERNANDEZ #clock-cells = <1>; 66be10afcdSGabriel FERNANDEZ compatible = "st,clkgena-plls-c65"; 67be10afcdSGabriel FERNANDEZ 680268099cSGabriel FERNANDEZ clocks = <&clk-sysin>; 69be10afcdSGabriel FERNANDEZ 700268099cSGabriel FERNANDEZ clock-output-names = "clk-s-a0-pll0-hs", 710268099cSGabriel FERNANDEZ "clk-s-a0-pll0-ls", 720268099cSGabriel FERNANDEZ "clk-s-a0-pll1"; 73be10afcdSGabriel FERNANDEZ }; 74be10afcdSGabriel FERNANDEZ 750268099cSGabriel FERNANDEZ clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { 76be10afcdSGabriel FERNANDEZ #clock-cells = <0>; 77be10afcdSGabriel FERNANDEZ compatible = "st,clkgena-prediv-c65", 78be10afcdSGabriel FERNANDEZ "st,clkgena-prediv"; 79be10afcdSGabriel FERNANDEZ 800268099cSGabriel FERNANDEZ clocks = <&clk_sysin>; 81be10afcdSGabriel FERNANDEZ 820268099cSGabriel FERNANDEZ clock-output-names = "clk-s-a0-osc-prediv"; 83be10afcdSGabriel FERNANDEZ }; 84be10afcdSGabriel FERNANDEZ 850268099cSGabriel FERNANDEZ clk_s_a0_hs: clk-s-a0-hs { 86be10afcdSGabriel FERNANDEZ #clock-cells = <1>; 87be10afcdSGabriel FERNANDEZ compatible = "st,clkgena-divmux-c65-hs", 88be10afcdSGabriel FERNANDEZ "st,clkgena-divmux"; 89be10afcdSGabriel FERNANDEZ 900268099cSGabriel FERNANDEZ clocks = <&clk-s_a0_osc_prediv>, 910268099cSGabriel FERNANDEZ <&clk-s_a0_pll 0>, /* pll0 hs */ 920268099cSGabriel FERNANDEZ <&clk-s_a0_pll 2>; /* pll1 */ 93be10afcdSGabriel FERNANDEZ 940268099cSGabriel FERNANDEZ clock-output-names = "clk-s-fdma-0", 950268099cSGabriel FERNANDEZ "clk-s-fdma-1", 960268099cSGabriel FERNANDEZ ""; /* clk-s-jit-sense */ 970268099cSGabriel FERNANDEZ /* fourth output unused */ 98be10afcdSGabriel FERNANDEZ }; 99be10afcdSGabriel FERNANDEZ }; 100be10afcdSGabriel FERNANDEZ 101