1be10afcdSGabriel FERNANDEZBinding for a Clockgen hardware block found on 2be10afcdSGabriel FERNANDEZcertain STMicroelectronics consumer electronics SoC devices. 3be10afcdSGabriel FERNANDEZ 4be10afcdSGabriel FERNANDEZA Clockgen node can contain pll, diviser or multiplexer nodes. 5be10afcdSGabriel FERNANDEZ 6be10afcdSGabriel FERNANDEZWe will find only the base address of the Clockgen, this base 7be10afcdSGabriel FERNANDEZaddress is common of all subnode. 8be10afcdSGabriel FERNANDEZ 9be10afcdSGabriel FERNANDEZ clockgen_node { 10be10afcdSGabriel FERNANDEZ reg = <>; 11be10afcdSGabriel FERNANDEZ 12be10afcdSGabriel FERNANDEZ pll_node { 13be10afcdSGabriel FERNANDEZ ... 14be10afcdSGabriel FERNANDEZ }; 15be10afcdSGabriel FERNANDEZ 16be10afcdSGabriel FERNANDEZ prediv_node { 17be10afcdSGabriel FERNANDEZ ... 18be10afcdSGabriel FERNANDEZ }; 19be10afcdSGabriel FERNANDEZ 20be10afcdSGabriel FERNANDEZ divmux_node { 21be10afcdSGabriel FERNANDEZ ... 22be10afcdSGabriel FERNANDEZ }; 23be10afcdSGabriel FERNANDEZ 24be10afcdSGabriel FERNANDEZ quadfs_node { 25be10afcdSGabriel FERNANDEZ ... 26be10afcdSGabriel FERNANDEZ }; 270268099cSGabriel FERNANDEZ 280268099cSGabriel FERNANDEZ mux_node { 290268099cSGabriel FERNANDEZ ... 300268099cSGabriel FERNANDEZ }; 310268099cSGabriel FERNANDEZ 320268099cSGabriel FERNANDEZ vcc_node { 330268099cSGabriel FERNANDEZ ... 340268099cSGabriel FERNANDEZ }; 35be10afcdSGabriel FERNANDEZ ... 36be10afcdSGabriel FERNANDEZ }; 37be10afcdSGabriel FERNANDEZ 38be10afcdSGabriel FERNANDEZThis binding uses the common clock binding[1]. 390268099cSGabriel FERNANDEZEach subnode should use the binding discribe in [2]..[7] 40be10afcdSGabriel FERNANDEZ 41be10afcdSGabriel FERNANDEZ[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 420268099cSGabriel FERNANDEZ[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt 430268099cSGabriel FERNANDEZ[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt 440268099cSGabriel FERNANDEZ[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt 450268099cSGabriel FERNANDEZ[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt 460268099cSGabriel FERNANDEZ[6] Documentation/devicetree/bindings/clock/st,vcc.txt 470268099cSGabriel FERNANDEZ[7] Documentation/devicetree/bindings/clock/st,quadfs.txt 480268099cSGabriel FERNANDEZ 49be10afcdSGabriel FERNANDEZ 50be10afcdSGabriel FERNANDEZRequired properties: 51be10afcdSGabriel FERNANDEZ- reg : A Base address and length of the register set. 52be10afcdSGabriel FERNANDEZ 53be10afcdSGabriel FERNANDEZExample: 54be10afcdSGabriel FERNANDEZ 550268099cSGabriel FERNANDEZ clockgen-a@fee62000 { 56be10afcdSGabriel FERNANDEZ 57be10afcdSGabriel FERNANDEZ reg = <0xfee62000 0xb48>; 58be10afcdSGabriel FERNANDEZ 590268099cSGabriel FERNANDEZ clk_s_a0_pll: clk-s-a0-pll { 60be10afcdSGabriel FERNANDEZ #clock-cells = <1>; 61be10afcdSGabriel FERNANDEZ compatible = "st,clkgena-plls-c65"; 62be10afcdSGabriel FERNANDEZ 630268099cSGabriel FERNANDEZ clocks = <&clk-sysin>; 64be10afcdSGabriel FERNANDEZ 650268099cSGabriel FERNANDEZ clock-output-names = "clk-s-a0-pll0-hs", 660268099cSGabriel FERNANDEZ "clk-s-a0-pll0-ls", 670268099cSGabriel FERNANDEZ "clk-s-a0-pll1"; 68be10afcdSGabriel FERNANDEZ }; 69be10afcdSGabriel FERNANDEZ 700268099cSGabriel FERNANDEZ clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { 71be10afcdSGabriel FERNANDEZ #clock-cells = <0>; 72be10afcdSGabriel FERNANDEZ compatible = "st,clkgena-prediv-c65", 73be10afcdSGabriel FERNANDEZ "st,clkgena-prediv"; 74be10afcdSGabriel FERNANDEZ 750268099cSGabriel FERNANDEZ clocks = <&clk_sysin>; 76be10afcdSGabriel FERNANDEZ 770268099cSGabriel FERNANDEZ clock-output-names = "clk-s-a0-osc-prediv"; 78be10afcdSGabriel FERNANDEZ }; 79be10afcdSGabriel FERNANDEZ 800268099cSGabriel FERNANDEZ clk_s_a0_hs: clk-s-a0-hs { 81be10afcdSGabriel FERNANDEZ #clock-cells = <1>; 82be10afcdSGabriel FERNANDEZ compatible = "st,clkgena-divmux-c65-hs", 83be10afcdSGabriel FERNANDEZ "st,clkgena-divmux"; 84be10afcdSGabriel FERNANDEZ 850268099cSGabriel FERNANDEZ clocks = <&clk-s_a0_osc_prediv>, 860268099cSGabriel FERNANDEZ <&clk-s_a0_pll 0>, /* pll0 hs */ 870268099cSGabriel FERNANDEZ <&clk-s_a0_pll 2>; /* pll1 */ 88be10afcdSGabriel FERNANDEZ 890268099cSGabriel FERNANDEZ clock-output-names = "clk-s-fdma-0", 900268099cSGabriel FERNANDEZ "clk-s-fdma-1", 910268099cSGabriel FERNANDEZ ""; /* clk-s-jit-sense */ 920268099cSGabriel FERNANDEZ /* fourth output unused */ 93be10afcdSGabriel FERNANDEZ }; 94be10afcdSGabriel FERNANDEZ }; 95be10afcdSGabriel FERNANDEZ 96