1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Reset Clock Controller Binding 8 9maintainers: 10 - Gabriel Fernandez <gabriel.fernandez@st.com> 11 12description: | 13 The RCC IP is both a reset and a clock controller. 14 RCC makes also power management (resume/supend and wakeup interrupt). 15 Please also refer to reset.txt for common reset controller binding usage. 16 17 This binding uses common clock bindings 18 Documentation/devicetree/bindings/clock/clock-bindings.txt 19 20 Specifying clocks 21 ================= 22 23 All available clocks are defined as preprocessor macros in 24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device 25 tree sources. 26 27 Specifying softreset control of devices 28 ======================================= 29 30 Device nodes should specify the reset channel required in their "resets" 31 property, containing a phandle to the reset device node and an index specifying 32 which channel to use. 33 The index is the bit number within the RCC registers bank, starting from RCC 34 base address. 35 It is calculated as: index = register_offset / 4 * 32 + bit_offset. 36 Where bit_offset is the bit offset within the register. 37 38 For example on STM32MP1, for LTDC reset: 39 ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset 40 = 0x180 / 4 * 32 + 0 = 3072 41 42 The list of valid indices for STM32MP1 is available in: 43 include/dt-bindings/reset-controller/stm32mp1-resets.h 44 45 This file implements defines like: 46 #define LTDC_R 3072 47 48properties: 49 "#clock-cells": 50 const: 1 51 52 "#reset-cells": 53 const: 1 54 55 compatible: 56 items: 57 - enum: 58 - st,stm32mp1-rcc-secure 59 - st,stm32mp1-rcc 60 - const: syscon 61 62 reg: 63 maxItems: 1 64 65required: 66 - "#clock-cells" 67 - "#reset-cells" 68 - compatible 69 - reg 70 71additionalProperties: false 72 73examples: 74 - | 75 rcc: rcc@50000000 { 76 compatible = "st,stm32mp1-rcc-secure", "syscon"; 77 reg = <0x50000000 0x1000>; 78 #clock-cells = <1>; 79 #reset-cells = <1>; 80 }; 81... 82