1STMicroelectronics STM32 Reset and Clock Controller
2===================================================
3
4The RCC IP is both a reset and a clock controller.
5
6Please refer to clock-bindings.txt for common clock controller binding usage.
7Please also refer to reset.txt for common reset controller binding usage.
8
9Required properties:
10- compatible: Should be "st,stm32f42xx-rcc"
11- reg: should be register base and length as documented in the
12  datasheet
13- #reset-cells: 1, see below
14- #clock-cells: 2, device nodes should specify the clock in their "clocks"
15  property, containing a phandle to the clock device node, an index selecting
16  between gated clocks and other clocks and an index specifying the clock to
17  use.
18
19Example:
20
21	rcc: rcc@40023800 {
22		#reset-cells = <1>;
23		#clock-cells = <2>
24		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
25		reg = <0x40023800 0x400>;
26	};
27
28Specifying gated clocks
29=======================
30
31The primary index must be set to 0.
32
33The secondary index is the bit number within the RCC register bank, starting
34from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
35
36It is calculated as: index = register_offset / 4 * 32 + bit_offset.
37Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
38
39To simplify the usage and to share bit definition with the reset and clock
40drivers of the RCC IP, macros are available to generate the index in
41human-readble format.
42
43For STM32F4 series, the macro are available here:
44 - include/dt-bindings/mfd/stm32f4-rcc.h
45
46Example:
47
48	/* Gated clock, AHB1 bit 0 (GPIOA) */
49	... {
50		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
51	};
52
53	/* Gated clock, AHB2 bit 4 (CRYP) */
54	... {
55		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
56	};
57
58Specifying other clocks
59=======================
60
61The primary index must be set to 1.
62
63The secondary index is bound with the following magic numbers:
64
65	0	SYSTICK
66	1	FCLK
67
68Example:
69
70	/* Misc clock, FCLK */
71	... {
72		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
73	};
74
75
76Specifying softreset control of devices
77=======================================
78
79Device nodes should specify the reset channel required in their "resets"
80property, containing a phandle to the reset device node and an index specifying
81which channel to use.
82The index is the bit number within the RCC registers bank, starting from RCC
83base address.
84It is calculated as: index = register_offset / 4 * 32 + bit_offset.
85Where bit_offset is the bit offset within the register.
86For example, for CRC reset:
87  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
88
89example:
90
91	timer2 {
92		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
93	};
94