1STMicroelectronics STM32 Reset and Clock Controller
2===================================================
3
4The RCC IP is both a reset and a clock controller.
5
6Please refer to clock-bindings.txt for common clock controller binding usage.
7Please also refer to reset.txt for common reset controller binding usage.
8
9Required properties:
10- compatible: Should be:
11  "st,stm32f42xx-rcc"
12  "st,stm32f469-rcc"
13  "st,stm32f746-rcc"
14- reg: should be register base and length as documented in the
15  datasheet
16- #reset-cells: 1, see below
17- #clock-cells: 2, device nodes should specify the clock in their "clocks"
18  property, containing a phandle to the clock device node, an index selecting
19  between gated clocks and other clocks and an index specifying the clock to
20  use.
21- clocks: External oscillator clock phandle
22  - high speed external clock signal (HSE)
23  - external I2S clock (I2S_CKIN)
24
25Example:
26
27	rcc: rcc@40023800 {
28		#reset-cells = <1>;
29		#clock-cells = <2>
30		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
31		reg = <0x40023800 0x400>;
32		clocks = <&clk_hse>, <&clk_i2s_ckin>;
33	};
34
35Specifying gated clocks
36=======================
37
38The primary index must be set to 0.
39
40The secondary index is the bit number within the RCC register bank, starting
41from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
42
43It is calculated as: index = register_offset / 4 * 32 + bit_offset.
44Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
45
46To simplify the usage and to share bit definition with the reset and clock
47drivers of the RCC IP, macros are available to generate the index in
48human-readble format.
49
50For STM32F4 series, the macro are available here:
51 - include/dt-bindings/mfd/stm32f4-rcc.h
52
53Example:
54
55	/* Gated clock, AHB1 bit 0 (GPIOA) */
56	... {
57		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
58	};
59
60	/* Gated clock, AHB2 bit 4 (CRYP) */
61	... {
62		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
63	};
64
65Specifying other clocks
66=======================
67
68The primary index must be set to 1.
69
70The secondary index is bound with the following magic numbers:
71
72	0	SYSTICK
73	1	FCLK
74	2	CLK_LSI		(low-power clock source)
75	3	CLK_LSE		(generated from a 32.768 kHz low-speed external
76				 crystal or ceramic resonator)
77	4	CLK_HSE_RTC	(HSE division factor for RTC clock)
78	5	CLK_RTC		(real-time clock)
79	6	PLL_VCO_I2S	(vco frequency of I2S pll)
80	7	PLL_VCO_SAI	(vco frequency of SAI pll)
81	8	CLK_LCD		(LCD-TFT)
82	9	CLK_I2S		(I2S clocks)
83	10	CLK_SAI1	(audio clocks)
84	11	CLK_SAI2
85	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)
86	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)
87
88	14	CLK_HSI		(Internal ocscillator clock)
89	15	CLK_SYSCLK	(System Clock)
90	16	CLK_HDMI_CEC	(HDMI-CEC clock)
91	17	CLK_SPDIF	(SPDIF-Rx clock)
92	18	CLK_USART1	(U(s)arts clocks)
93	19	CLK_USART2
94	20	CLK_USART3
95	21	CLK_UART4
96	22	CLK_UART5
97	23	CLK_USART6
98	24	CLK_UART7
99	25	CLK_UART8
100	26	CLK_I2C1	(I2S clocks)
101	27	CLK_I2C2
102	28	CLK_I2C3
103	29	CLK_I2C4
104	30	CLK_LPTIMER	(LPTimer1 clock)
105)
106
107Example:
108
109	/* Misc clock, FCLK */
110	... {
111		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
112	};
113
114
115Specifying softreset control of devices
116=======================================
117
118Device nodes should specify the reset channel required in their "resets"
119property, containing a phandle to the reset device node and an index specifying
120which channel to use.
121The index is the bit number within the RCC registers bank, starting from RCC
122base address.
123It is calculated as: index = register_offset / 4 * 32 + bit_offset.
124Where bit_offset is the bit offset within the register.
125For example, for CRC reset:
126  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
127
128example:
129
130	timer2 {
131		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
132	};
133