1*6a3a6c7aSCixi Geng# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*6a3a6c7aSCixi Geng# Copyright 2022 Unisoc Inc.
3*6a3a6c7aSCixi Geng%YAML 1.2
4*6a3a6c7aSCixi Geng---
5*6a3a6c7aSCixi Geng$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
6*6a3a6c7aSCixi Geng$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7*6a3a6c7aSCixi Geng
8*6a3a6c7aSCixi Gengtitle: UMS512 Soc clock controller
9*6a3a6c7aSCixi Geng
10*6a3a6c7aSCixi Gengmaintainers:
11*6a3a6c7aSCixi Geng  - Orson Zhai <orsonzhai@gmail.com>
12*6a3a6c7aSCixi Geng  - Baolin Wang <baolin.wang7@gmail.com>
13*6a3a6c7aSCixi Geng  - Chunyan Zhang <zhang.lyra@gmail.com>
14*6a3a6c7aSCixi Geng
15*6a3a6c7aSCixi Gengproperties:
16*6a3a6c7aSCixi Geng  compatible:
17*6a3a6c7aSCixi Geng    enum:
18*6a3a6c7aSCixi Geng      - sprd,ums512-apahb-gate
19*6a3a6c7aSCixi Geng      - sprd,ums512-ap-clk
20*6a3a6c7aSCixi Geng      - sprd,ums512-aonapb-clk
21*6a3a6c7aSCixi Geng      - sprd,ums512-pmu-gate
22*6a3a6c7aSCixi Geng      - sprd,ums512-g0-pll
23*6a3a6c7aSCixi Geng      - sprd,ums512-g2-pll
24*6a3a6c7aSCixi Geng      - sprd,ums512-g3-pll
25*6a3a6c7aSCixi Geng      - sprd,ums512-gc-pll
26*6a3a6c7aSCixi Geng      - sprd,ums512-aon-gate
27*6a3a6c7aSCixi Geng      - sprd,ums512-audcpapb-gate
28*6a3a6c7aSCixi Geng      - sprd,ums512-audcpahb-gate
29*6a3a6c7aSCixi Geng      - sprd,ums512-gpu-clk
30*6a3a6c7aSCixi Geng      - sprd,ums512-mm-clk
31*6a3a6c7aSCixi Geng      - sprd,ums512-mm-gate-clk
32*6a3a6c7aSCixi Geng      - sprd,ums512-apapb-gate
33*6a3a6c7aSCixi Geng
34*6a3a6c7aSCixi Geng  "#clock-cells":
35*6a3a6c7aSCixi Geng    const: 1
36*6a3a6c7aSCixi Geng
37*6a3a6c7aSCixi Geng  clocks:
38*6a3a6c7aSCixi Geng    minItems: 1
39*6a3a6c7aSCixi Geng    maxItems: 4
40*6a3a6c7aSCixi Geng    description: |
41*6a3a6c7aSCixi Geng      The input parent clock(s) phandle for the clock, only list
42*6a3a6c7aSCixi Geng      fixed clocks which are declared in devicetree.
43*6a3a6c7aSCixi Geng
44*6a3a6c7aSCixi Geng  clock-names:
45*6a3a6c7aSCixi Geng    minItems: 1
46*6a3a6c7aSCixi Geng    items:
47*6a3a6c7aSCixi Geng      - const: ext-26m
48*6a3a6c7aSCixi Geng      - const: ext-32k
49*6a3a6c7aSCixi Geng      - const: ext-4m
50*6a3a6c7aSCixi Geng      - const: rco-100m
51*6a3a6c7aSCixi Geng
52*6a3a6c7aSCixi Geng  reg:
53*6a3a6c7aSCixi Geng    maxItems: 1
54*6a3a6c7aSCixi Geng
55*6a3a6c7aSCixi Gengrequired:
56*6a3a6c7aSCixi Geng  - compatible
57*6a3a6c7aSCixi Geng  - '#clock-cells'
58*6a3a6c7aSCixi Geng  - reg
59*6a3a6c7aSCixi Geng
60*6a3a6c7aSCixi GengadditionalProperties: false
61*6a3a6c7aSCixi Geng
62*6a3a6c7aSCixi Gengexamples:
63*6a3a6c7aSCixi Geng  - |
64*6a3a6c7aSCixi Geng    ap_clk: clock-controller@20200000 {
65*6a3a6c7aSCixi Geng      compatible = "sprd,ums512-ap-clk";
66*6a3a6c7aSCixi Geng      reg = <0x20200000 0x1000>;
67*6a3a6c7aSCixi Geng      clocks = <&ext_26m>;
68*6a3a6c7aSCixi Geng      clock-names = "ext-26m";
69*6a3a6c7aSCixi Geng      #clock-cells = <1>;
70*6a3a6c7aSCixi Geng    };
71*6a3a6c7aSCixi Geng...
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