1eba8ba8aSChunyan Zhang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2eba8ba8aSChunyan Zhang# Copyright 2019 Unisoc Inc. 3eba8ba8aSChunyan Zhang%YAML 1.2 4eba8ba8aSChunyan Zhang--- 5eba8ba8aSChunyan Zhang$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#" 6eba8ba8aSChunyan Zhang$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7eba8ba8aSChunyan Zhang 8eba8ba8aSChunyan Zhangtitle: SC9863A Clock Control Unit Device Tree Bindings 9eba8ba8aSChunyan Zhang 10eba8ba8aSChunyan Zhangmaintainers: 11eba8ba8aSChunyan Zhang - Orson Zhai <orsonzhai@gmail.com> 12eba8ba8aSChunyan Zhang - Baolin Wang <baolin.wang7@gmail.com> 13eba8ba8aSChunyan Zhang - Chunyan Zhang <zhang.lyra@gmail.com> 14eba8ba8aSChunyan Zhang 15eba8ba8aSChunyan Zhangproperties: 16eba8ba8aSChunyan Zhang "#clock-cells": 17eba8ba8aSChunyan Zhang const: 1 18eba8ba8aSChunyan Zhang 19eba8ba8aSChunyan Zhang compatible : 20eba8ba8aSChunyan Zhang enum: 21eba8ba8aSChunyan Zhang - sprd,sc9863a-ap-clk 22eba8ba8aSChunyan Zhang - sprd,sc9863a-aon-clk 23eba8ba8aSChunyan Zhang - sprd,sc9863a-apahb-gate 24eba8ba8aSChunyan Zhang - sprd,sc9863a-pmu-gate 25eba8ba8aSChunyan Zhang - sprd,sc9863a-aonapb-gate 26eba8ba8aSChunyan Zhang - sprd,sc9863a-pll 27eba8ba8aSChunyan Zhang - sprd,sc9863a-mpll 28eba8ba8aSChunyan Zhang - sprd,sc9863a-rpll 29eba8ba8aSChunyan Zhang - sprd,sc9863a-dpll 30eba8ba8aSChunyan Zhang - sprd,sc9863a-mm-gate 3182a4d4a7SChunyan Zhang - sprd,sc9863a-mm-clk 32eba8ba8aSChunyan Zhang - sprd,sc9863a-apapb-gate 33eba8ba8aSChunyan Zhang 34eba8ba8aSChunyan Zhang clocks: 35eba8ba8aSChunyan Zhang minItems: 1 36eba8ba8aSChunyan Zhang maxItems: 4 37eba8ba8aSChunyan Zhang description: | 38eba8ba8aSChunyan Zhang The input parent clock(s) phandle for this clock, only list fixed 39eba8ba8aSChunyan Zhang clocks which are declared in devicetree. 40eba8ba8aSChunyan Zhang 41eba8ba8aSChunyan Zhang clock-names: 42eba8ba8aSChunyan Zhang minItems: 1 43eba8ba8aSChunyan Zhang maxItems: 4 44eba8ba8aSChunyan Zhang items: 45eba8ba8aSChunyan Zhang - const: ext-26m 46eba8ba8aSChunyan Zhang - const: ext-32k 47eba8ba8aSChunyan Zhang - const: ext-4m 48eba8ba8aSChunyan Zhang - const: rco-100m 49eba8ba8aSChunyan Zhang 50eba8ba8aSChunyan Zhang reg: 51eba8ba8aSChunyan Zhang maxItems: 1 52eba8ba8aSChunyan Zhang 53eba8ba8aSChunyan Zhangrequired: 54eba8ba8aSChunyan Zhang - compatible 55eba8ba8aSChunyan Zhang - '#clock-cells' 56eba8ba8aSChunyan Zhang 57eba8ba8aSChunyan Zhangif: 58eba8ba8aSChunyan Zhang properties: 59eba8ba8aSChunyan Zhang compatible: 60eba8ba8aSChunyan Zhang enum: 61eba8ba8aSChunyan Zhang - sprd,sc9863a-ap-clk 62eba8ba8aSChunyan Zhang - sprd,sc9863a-aon-clk 63eba8ba8aSChunyan Zhangthen: 64eba8ba8aSChunyan Zhang required: 65eba8ba8aSChunyan Zhang - reg 66eba8ba8aSChunyan Zhang 67eba8ba8aSChunyan Zhangelse: 68eba8ba8aSChunyan Zhang description: | 69eba8ba8aSChunyan Zhang Other SC9863a clock nodes should be the child of a syscon node in 70eba8ba8aSChunyan Zhang which compatible string shoule be: 71eba8ba8aSChunyan Zhang "sprd,sc9863a-glbregs", "syscon", "simple-mfd" 72eba8ba8aSChunyan Zhang 73eba8ba8aSChunyan Zhang The 'reg' property for the clock node is also required if there is a sub 74eba8ba8aSChunyan Zhang range of registers for the clocks. 75eba8ba8aSChunyan Zhang 76eba8ba8aSChunyan Zhangexamples: 77eba8ba8aSChunyan Zhang - | 78eba8ba8aSChunyan Zhang ap_clk: clock-controller@21500000 { 79eba8ba8aSChunyan Zhang compatible = "sprd,sc9863a-ap-clk"; 80eba8ba8aSChunyan Zhang reg = <0 0x21500000 0 0x1000>; 81eba8ba8aSChunyan Zhang clocks = <&ext_26m>, <&ext_32k>; 82eba8ba8aSChunyan Zhang clock-names = "ext-26m", "ext-32k"; 83eba8ba8aSChunyan Zhang #clock-cells = <1>; 84eba8ba8aSChunyan Zhang }; 85eba8ba8aSChunyan Zhang 86eba8ba8aSChunyan Zhang - | 87eba8ba8aSChunyan Zhang soc { 88eba8ba8aSChunyan Zhang #address-cells = <2>; 89eba8ba8aSChunyan Zhang #size-cells = <2>; 90eba8ba8aSChunyan Zhang 91eba8ba8aSChunyan Zhang ap_ahb_regs: syscon@20e00000 { 92eba8ba8aSChunyan Zhang compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; 93eba8ba8aSChunyan Zhang reg = <0 0x20e00000 0 0x4000>; 94eba8ba8aSChunyan Zhang #address-cells = <1>; 95eba8ba8aSChunyan Zhang #size-cells = <1>; 96eba8ba8aSChunyan Zhang ranges = <0 0 0x20e00000 0x4000>; 97eba8ba8aSChunyan Zhang 98eba8ba8aSChunyan Zhang apahb_gate: apahb-gate@0 { 99eba8ba8aSChunyan Zhang compatible = "sprd,sc9863a-apahb-gate"; 100eba8ba8aSChunyan Zhang reg = <0x0 0x1020>; 101eba8ba8aSChunyan Zhang #clock-cells = <1>; 102eba8ba8aSChunyan Zhang }; 103eba8ba8aSChunyan Zhang }; 104eba8ba8aSChunyan Zhang }; 105eba8ba8aSChunyan Zhang 106eba8ba8aSChunyan Zhang... 107