1Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
2
3Reference
4[1] Si5351A/B/C Data Sheet
5    http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
6
7The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
93 output clocks are accessible. The internal structure of the clock
10generators can be found in [1].
11
12==I2C device node==
13
14Required properties:
15- compatible: shall be one of the following:
16	"silabs,si5351a" - Si5351a, QFN20 package
17	"silabs,si5351a-msop" - Si5351a, MSOP10 package
18	"silabs,si5351b" - Si5351b, QFN20 package
19	"silabs,si5351c" - Si5351c, QFN20 package
20- reg: i2c device address, shall be 0x60 or 0x61.
21- #clock-cells: from common clock binding; shall be set to 1.
22- clocks: from common clock binding; list of parent clock
23  handles, shall be xtal reference clock or xtal and clkin for
24  si5351c only. Corresponding clock input names are "xtal" and
25  "clkin" respectively.
26- #address-cells: shall be set to 1.
27- #size-cells: shall be set to 0.
28
29Optional properties:
30- silabs,pll-source: pair of (number, source) for each pll. Allows
31  to overwrite clock source of pll A (number=0) or B (number=1).
32
33==Child nodes==
34
35Each of the clock outputs can be overwritten individually by
36using a child node to the I2C device node. If a child node for a clock
37output is not set, the eeprom configuration is not overwritten.
38
39Required child node properties:
40- reg: number of clock output.
41
42Optional child node properties:
43- silabs,clock-source: source clock of the output divider stage N, shall be
44  0 = multisynth N
45  1 = multisynth 0 for output clocks 0-3, else multisynth4
46  2 = xtal
47  3 = clkin (si5351c only)
48- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
49- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
50  divider.
51- silabs,pll-master: boolean, multisynth can change pll frequency.
52- silabs,disable-state : clock output disable state, shall be
53  0 = clock output is driven LOW when disabled
54  1 = clock output is driven HIGH when disabled
55  2 = clock output is FLOATING (HIGH-Z) when disabled
56  3 = clock output is NEVER disabled
57
58==Example==
59
60/* 25MHz reference crystal */
61ref25: ref25M {
62	compatible = "fixed-clock";
63	#clock-cells = <0>;
64	clock-frequency = <25000000>;
65};
66
67i2c-master-node {
68
69	/* Si5351a msop10 i2c clock generator */
70	si5351a: clock-generator@60 {
71		compatible = "silabs,si5351a-msop";
72		reg = <0x60>;
73		#address-cells = <1>;
74		#size-cells = <0>;
75		#clock-cells = <1>;
76
77		/* connect xtal input to 25MHz reference */
78		clocks = <&ref25>;
79		clock-names = "xtal";
80
81		/* connect xtal input as source of pll0 and pll1 */
82		silabs,pll-source = <0 0>, <1 0>;
83
84		/*
85		 * overwrite clkout0 configuration with:
86		 * - 8mA output drive strength
87		 * - pll0 as clock source of multisynth0
88		 * - multisynth0 as clock source of output divider
89		 * - multisynth0 can change pll0
90		 * - set initial clock frequency of 74.25MHz
91		 */
92		clkout0 {
93			reg = <0>;
94			silabs,drive-strength = <8>;
95			silabs,multisynth-source = <0>;
96			silabs,clock-source = <0>;
97			silabs,pll-master;
98			clock-frequency = <74250000>;
99		};
100
101		/*
102		 * overwrite clkout1 configuration with:
103		 * - 4mA output drive strength
104		 * - pll1 as clock source of multisynth1
105		 * - multisynth1 as clock source of output divider
106		 * - multisynth1 can change pll1
107		 */
108		clkout1 {
109			reg = <1>;
110			silabs,drive-strength = <4>;
111			silabs,multisynth-source = <1>;
112			silabs,clock-source = <0>;
113			pll-master;
114		};
115
116		/*
117		 * overwrite clkout2 configuration with:
118		 * - xtal as clock source of output divider
119		 */
120		clkout2 {
121			reg = <2>;
122			silabs,clock-source = <2>;
123		};
124	};
125};
126