1*77624aa1SDavid Virag# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*77624aa1SDavid Virag%YAML 1.2
3*77624aa1SDavid Virag---
4*77624aa1SDavid Virag$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
5*77624aa1SDavid Virag$schema: http://devicetree.org/meta-schemas/core.yaml#
6*77624aa1SDavid Virag
7*77624aa1SDavid Viragtitle: Samsung Exynos7885 SoC clock controller
8*77624aa1SDavid Virag
9*77624aa1SDavid Viragmaintainers:
10*77624aa1SDavid Virag  - Dávid Virág <virag.david003@gmail.com>
11*77624aa1SDavid Virag  - Chanwoo Choi <cw00.choi@samsung.com>
12*77624aa1SDavid Virag  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13*77624aa1SDavid Virag  - Sylwester Nawrocki <s.nawrocki@samsung.com>
14*77624aa1SDavid Virag  - Tomasz Figa <tomasz.figa@gmail.com>
15*77624aa1SDavid Virag
16*77624aa1SDavid Viragdescription: |
17*77624aa1SDavid Virag  Exynos7885 clock controller is comprised of several CMU units, generating
18*77624aa1SDavid Virag  clocks for different domains. Those CMU units are modeled as separate device
19*77624aa1SDavid Virag  tree nodes, and might depend on each other. The root clock in that root tree
20*77624aa1SDavid Virag  is an external clock: OSCCLK (26 MHz). This external clock must be defined
21*77624aa1SDavid Virag  as a fixed-rate clock in dts.
22*77624aa1SDavid Virag
23*77624aa1SDavid Virag  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24*77624aa1SDavid Virag  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
25*77624aa1SDavid Virag
26*77624aa1SDavid Virag  Each clock is assigned an identifier and client nodes can use this identifier
27*77624aa1SDavid Virag  to specify the clock which they consume. All clocks available for usage
28*77624aa1SDavid Virag  in clock consumer nodes are defined as preprocessor macros in
29*77624aa1SDavid Virag  'dt-bindings/clock/exynos7885.h' header.
30*77624aa1SDavid Virag
31*77624aa1SDavid Viragproperties:
32*77624aa1SDavid Virag  compatible:
33*77624aa1SDavid Virag    enum:
34*77624aa1SDavid Virag      - samsung,exynos7885-cmu-top
35*77624aa1SDavid Virag      - samsung,exynos7885-cmu-core
36*77624aa1SDavid Virag      - samsung,exynos7885-cmu-peri
37*77624aa1SDavid Virag
38*77624aa1SDavid Virag  clocks:
39*77624aa1SDavid Virag    minItems: 1
40*77624aa1SDavid Virag    maxItems: 10
41*77624aa1SDavid Virag
42*77624aa1SDavid Virag  clock-names:
43*77624aa1SDavid Virag    minItems: 1
44*77624aa1SDavid Virag    maxItems: 10
45*77624aa1SDavid Virag
46*77624aa1SDavid Virag  "#clock-cells":
47*77624aa1SDavid Virag    const: 1
48*77624aa1SDavid Virag
49*77624aa1SDavid Virag  reg:
50*77624aa1SDavid Virag    maxItems: 1
51*77624aa1SDavid Virag
52*77624aa1SDavid ViragallOf:
53*77624aa1SDavid Virag  - if:
54*77624aa1SDavid Virag      properties:
55*77624aa1SDavid Virag        compatible:
56*77624aa1SDavid Virag          contains:
57*77624aa1SDavid Virag            const: samsung,exynos7885-cmu-top
58*77624aa1SDavid Virag
59*77624aa1SDavid Virag    then:
60*77624aa1SDavid Virag      properties:
61*77624aa1SDavid Virag        clocks:
62*77624aa1SDavid Virag          items:
63*77624aa1SDavid Virag            - description: External reference clock (26 MHz)
64*77624aa1SDavid Virag
65*77624aa1SDavid Virag        clock-names:
66*77624aa1SDavid Virag          items:
67*77624aa1SDavid Virag            - const: oscclk
68*77624aa1SDavid Virag
69*77624aa1SDavid Virag  - if:
70*77624aa1SDavid Virag      properties:
71*77624aa1SDavid Virag        compatible:
72*77624aa1SDavid Virag          contains:
73*77624aa1SDavid Virag            const: samsung,exynos7885-cmu-core
74*77624aa1SDavid Virag
75*77624aa1SDavid Virag    then:
76*77624aa1SDavid Virag      properties:
77*77624aa1SDavid Virag        clocks:
78*77624aa1SDavid Virag          items:
79*77624aa1SDavid Virag            - description: External reference clock (26 MHz)
80*77624aa1SDavid Virag            - description: CMU_CORE bus clock (from CMU_TOP)
81*77624aa1SDavid Virag            - description: CCI clock (from CMU_TOP)
82*77624aa1SDavid Virag            - description: G3D clock (from CMU_TOP)
83*77624aa1SDavid Virag
84*77624aa1SDavid Virag        clock-names:
85*77624aa1SDavid Virag          items:
86*77624aa1SDavid Virag            - const: oscclk
87*77624aa1SDavid Virag            - const: dout_core_bus
88*77624aa1SDavid Virag            - const: dout_core_cci
89*77624aa1SDavid Virag            - const: dout_core_g3d
90*77624aa1SDavid Virag
91*77624aa1SDavid Virag  - if:
92*77624aa1SDavid Virag      properties:
93*77624aa1SDavid Virag        compatible:
94*77624aa1SDavid Virag          contains:
95*77624aa1SDavid Virag            const: samsung,exynos7885-cmu-peri
96*77624aa1SDavid Virag
97*77624aa1SDavid Virag    then:
98*77624aa1SDavid Virag      properties:
99*77624aa1SDavid Virag        clocks:
100*77624aa1SDavid Virag          items:
101*77624aa1SDavid Virag            - description: External reference clock (26 MHz)
102*77624aa1SDavid Virag            - description: CMU_PERI bus clock (from CMU_TOP)
103*77624aa1SDavid Virag            - description: SPI0 clock (from CMU_TOP)
104*77624aa1SDavid Virag            - description: SPI1 clock (from CMU_TOP)
105*77624aa1SDavid Virag            - description: UART0 clock (from CMU_TOP)
106*77624aa1SDavid Virag            - description: UART1 clock (from CMU_TOP)
107*77624aa1SDavid Virag            - description: UART2 clock (from CMU_TOP)
108*77624aa1SDavid Virag            - description: USI0 clock (from CMU_TOP)
109*77624aa1SDavid Virag            - description: USI1 clock (from CMU_TOP)
110*77624aa1SDavid Virag            - description: USI2 clock (from CMU_TOP)
111*77624aa1SDavid Virag
112*77624aa1SDavid Virag        clock-names:
113*77624aa1SDavid Virag          items:
114*77624aa1SDavid Virag            - const: oscclk
115*77624aa1SDavid Virag            - const: dout_peri_bus
116*77624aa1SDavid Virag            - const: dout_peri_spi0
117*77624aa1SDavid Virag            - const: dout_peri_spi1
118*77624aa1SDavid Virag            - const: dout_peri_uart0
119*77624aa1SDavid Virag            - const: dout_peri_uart1
120*77624aa1SDavid Virag            - const: dout_peri_uart2
121*77624aa1SDavid Virag            - const: dout_peri_usi0
122*77624aa1SDavid Virag            - const: dout_peri_usi1
123*77624aa1SDavid Virag            - const: dout_peri_usi2
124*77624aa1SDavid Virag
125*77624aa1SDavid Viragrequired:
126*77624aa1SDavid Virag  - compatible
127*77624aa1SDavid Virag  - "#clock-cells"
128*77624aa1SDavid Virag  - clocks
129*77624aa1SDavid Virag  - clock-names
130*77624aa1SDavid Virag  - reg
131*77624aa1SDavid Virag
132*77624aa1SDavid ViragadditionalProperties: false
133*77624aa1SDavid Virag
134*77624aa1SDavid Viragexamples:
135*77624aa1SDavid Virag  # Clock controller node for CMU_PERI
136*77624aa1SDavid Virag  - |
137*77624aa1SDavid Virag    #include <dt-bindings/clock/exynos7885.h>
138*77624aa1SDavid Virag
139*77624aa1SDavid Virag    cmu_peri: clock-controller@10010000 {
140*77624aa1SDavid Virag        compatible = "samsung,exynos7885-cmu-peri";
141*77624aa1SDavid Virag        reg = <0x10010000 0x8000>;
142*77624aa1SDavid Virag        #clock-cells = <1>;
143*77624aa1SDavid Virag
144*77624aa1SDavid Virag        clocks = <&oscclk>,
145*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_BUS>,
146*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_SPI0>,
147*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_SPI1>,
148*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_UART0>,
149*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_UART1>,
150*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_UART2>,
151*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_USI0>,
152*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_USI1>,
153*77624aa1SDavid Virag                 <&cmu_top CLK_DOUT_PERI_USI2>;
154*77624aa1SDavid Virag        clock-names = "oscclk",
155*77624aa1SDavid Virag                      "dout_peri_bus",
156*77624aa1SDavid Virag                      "dout_peri_spi0",
157*77624aa1SDavid Virag                      "dout_peri_spi1",
158*77624aa1SDavid Virag                      "dout_peri_uart0",
159*77624aa1SDavid Virag                      "dout_peri_uart1",
160*77624aa1SDavid Virag                      "dout_peri_uart2",
161*77624aa1SDavid Virag                      "dout_peri_usi0",
162*77624aa1SDavid Virag                      "dout_peri_usi1",
163*77624aa1SDavid Virag                      "dout_peri_usi2";
164*77624aa1SDavid Virag    };
165*77624aa1SDavid Virag
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