1*fffa0fa4SJohan Jonker# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
25eb60b7bSJohan Jonker%YAML 1.2
35eb60b7bSJohan Jonker---
45eb60b7bSJohan Jonker$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
55eb60b7bSJohan Jonker$schema: http://devicetree.org/meta-schemas/core.yaml#
65eb60b7bSJohan Jonker
75eb60b7bSJohan Jonkertitle: Rockchip RV1108 Clock and Reset Unit (CRU)
85eb60b7bSJohan Jonker
95eb60b7bSJohan Jonkermaintainers:
105eb60b7bSJohan Jonker  - Elaine Zhang <zhangqing@rock-chips.com>
115eb60b7bSJohan Jonker  - Heiko Stuebner <heiko@sntech.de>
125eb60b7bSJohan Jonker
135eb60b7bSJohan Jonkerdescription: |
145eb60b7bSJohan Jonker  The RV1108 clock controller generates and supplies clocks to various
155eb60b7bSJohan Jonker  controllers within the SoC and also implements a reset controller for SoC
165eb60b7bSJohan Jonker  peripherals.
175eb60b7bSJohan Jonker  Each clock is assigned an identifier and client nodes can use this identifier
185eb60b7bSJohan Jonker  to specify the clock which they consume. All available clocks are defined as
195eb60b7bSJohan Jonker  preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
205eb60b7bSJohan Jonker  used in device tree sources. Similar macros exist for the reset sources in
215eb60b7bSJohan Jonker  these files.
225eb60b7bSJohan Jonker  There are several clocks that are generated outside the SoC. It is expected
235eb60b7bSJohan Jonker  that they are defined using standard clock bindings with following
245eb60b7bSJohan Jonker  clock-output-names:
255eb60b7bSJohan Jonker    - "xin24m"   - crystal input                              - required
265eb60b7bSJohan Jonker    - "ext_vip"  - external VIP clock                         - optional
275eb60b7bSJohan Jonker    - "ext_i2s"  - external I2S clock                         - optional
285eb60b7bSJohan Jonker    - "ext_gmac" - external GMAC clock                        - optional
295eb60b7bSJohan Jonker    - "hdmiphy"  - external clock input derived from HDMI PHY - optional
305eb60b7bSJohan Jonker    - "usbphy"   - external clock input derived from USB PHY  - optional
315eb60b7bSJohan Jonker
325eb60b7bSJohan Jonkerproperties:
335eb60b7bSJohan Jonker  compatible:
345eb60b7bSJohan Jonker    enum:
355eb60b7bSJohan Jonker      - rockchip,rv1108-cru
365eb60b7bSJohan Jonker
375eb60b7bSJohan Jonker  reg:
385eb60b7bSJohan Jonker    maxItems: 1
395eb60b7bSJohan Jonker
405eb60b7bSJohan Jonker  "#clock-cells":
415eb60b7bSJohan Jonker    const: 1
425eb60b7bSJohan Jonker
435eb60b7bSJohan Jonker  "#reset-cells":
445eb60b7bSJohan Jonker    const: 1
455eb60b7bSJohan Jonker
465eb60b7bSJohan Jonker  clocks:
475eb60b7bSJohan Jonker    maxItems: 1
485eb60b7bSJohan Jonker
495eb60b7bSJohan Jonker  clock-names:
505eb60b7bSJohan Jonker    const: xin24m
515eb60b7bSJohan Jonker
525eb60b7bSJohan Jonker  rockchip,grf:
535eb60b7bSJohan Jonker    $ref: /schemas/types.yaml#/definitions/phandle
545eb60b7bSJohan Jonker    description:
555eb60b7bSJohan Jonker      Phandle to the syscon managing the "general register files" (GRF),
565eb60b7bSJohan Jonker      if missing pll rates are not changeable, due to the missing pll
575eb60b7bSJohan Jonker      lock status.
585eb60b7bSJohan Jonker
595eb60b7bSJohan Jonkerrequired:
605eb60b7bSJohan Jonker  - compatible
615eb60b7bSJohan Jonker  - reg
625eb60b7bSJohan Jonker  - "#clock-cells"
635eb60b7bSJohan Jonker  - "#reset-cells"
645eb60b7bSJohan Jonker
655eb60b7bSJohan JonkeradditionalProperties: false
665eb60b7bSJohan Jonker
675eb60b7bSJohan Jonkerexamples:
685eb60b7bSJohan Jonker  - |
695eb60b7bSJohan Jonker    cru: clock-controller@20200000 {
705eb60b7bSJohan Jonker      compatible = "rockchip,rv1108-cru";
715eb60b7bSJohan Jonker      reg = <0x20200000 0x1000>;
725eb60b7bSJohan Jonker      rockchip,grf = <&grf>;
735eb60b7bSJohan Jonker      #clock-cells = <1>;
745eb60b7bSJohan Jonker      #reset-cells = <1>;
755eb60b7bSJohan Jonker    };
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