1*4f5ca304SElaine Zhang# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*4f5ca304SElaine Zhang%YAML 1.2 3*4f5ca304SElaine Zhang--- 4*4f5ca304SElaine Zhang$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml# 5*4f5ca304SElaine Zhang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4f5ca304SElaine Zhang 7*4f5ca304SElaine Zhangtitle: Rockchip rk3588 Family Clock and Reset Control Module 8*4f5ca304SElaine Zhang 9*4f5ca304SElaine Zhangmaintainers: 10*4f5ca304SElaine Zhang - Elaine Zhang <zhangqing@rock-chips.com> 11*4f5ca304SElaine Zhang - Heiko Stuebner <heiko@sntech.de> 12*4f5ca304SElaine Zhang 13*4f5ca304SElaine Zhangdescription: | 14*4f5ca304SElaine Zhang The RK3588 clock controller generates the clock and also implements a reset 15*4f5ca304SElaine Zhang controller for SoC peripherals. For example it provides SCLK_UART2 and 16*4f5ca304SElaine Zhang PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART 17*4f5ca304SElaine Zhang module. 18*4f5ca304SElaine Zhang Each clock is assigned an identifier and client nodes can use this identifier 19*4f5ca304SElaine Zhang to specify the clock which they consume. All available clock and reset IDs 20*4f5ca304SElaine Zhang are defined as preprocessor macros in dt-binding headers. 21*4f5ca304SElaine Zhang 22*4f5ca304SElaine Zhangproperties: 23*4f5ca304SElaine Zhang compatible: 24*4f5ca304SElaine Zhang enum: 25*4f5ca304SElaine Zhang - rockchip,rk3588-cru 26*4f5ca304SElaine Zhang 27*4f5ca304SElaine Zhang reg: 28*4f5ca304SElaine Zhang maxItems: 1 29*4f5ca304SElaine Zhang 30*4f5ca304SElaine Zhang "#clock-cells": 31*4f5ca304SElaine Zhang const: 1 32*4f5ca304SElaine Zhang 33*4f5ca304SElaine Zhang "#reset-cells": 34*4f5ca304SElaine Zhang const: 1 35*4f5ca304SElaine Zhang 36*4f5ca304SElaine Zhang clocks: 37*4f5ca304SElaine Zhang minItems: 2 38*4f5ca304SElaine Zhang maxItems: 2 39*4f5ca304SElaine Zhang 40*4f5ca304SElaine Zhang clock-names: 41*4f5ca304SElaine Zhang items: 42*4f5ca304SElaine Zhang - const: xin24m 43*4f5ca304SElaine Zhang - const: xin32k 44*4f5ca304SElaine Zhang 45*4f5ca304SElaine Zhang assigned-clocks: true 46*4f5ca304SElaine Zhang 47*4f5ca304SElaine Zhang assigned-clock-rates: true 48*4f5ca304SElaine Zhang 49*4f5ca304SElaine Zhang rockchip,grf: 50*4f5ca304SElaine Zhang $ref: /schemas/types.yaml#/definitions/phandle 51*4f5ca304SElaine Zhang description: > 52*4f5ca304SElaine Zhang phandle to the syscon managing the "general register files". It is used 53*4f5ca304SElaine Zhang for GRF muxes, if missing any muxes present in the GRF will not be 54*4f5ca304SElaine Zhang available. 55*4f5ca304SElaine Zhang 56*4f5ca304SElaine Zhangrequired: 57*4f5ca304SElaine Zhang - compatible 58*4f5ca304SElaine Zhang - reg 59*4f5ca304SElaine Zhang - "#clock-cells" 60*4f5ca304SElaine Zhang - "#reset-cells" 61*4f5ca304SElaine Zhang 62*4f5ca304SElaine ZhangadditionalProperties: false 63*4f5ca304SElaine Zhang 64*4f5ca304SElaine Zhangexamples: 65*4f5ca304SElaine Zhang - | 66*4f5ca304SElaine Zhang cru: clock-controller@fd7c0000 { 67*4f5ca304SElaine Zhang compatible = "rockchip,rk3588-cru"; 68*4f5ca304SElaine Zhang reg = <0xfd7c0000 0x5c000>; 69*4f5ca304SElaine Zhang #clock-cells = <1>; 70*4f5ca304SElaine Zhang #reset-cells = <1>; 71*4f5ca304SElaine Zhang }; 72