1*32a214cdSJohan Jonker# SPDX-License-Identifier: GPL-2.0 2*32a214cdSJohan Jonker%YAML 1.2 3*32a214cdSJohan Jonker--- 4*32a214cdSJohan Jonker$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml# 5*32a214cdSJohan Jonker$schema: http://devicetree.org/meta-schemas/core.yaml# 6*32a214cdSJohan Jonker 7*32a214cdSJohan Jonkertitle: Rockchip RK3368 Clock and Reset Unit (CRU) 8*32a214cdSJohan Jonker 9*32a214cdSJohan Jonkermaintainers: 10*32a214cdSJohan Jonker - Elaine Zhang <zhangqing@rock-chips.com> 11*32a214cdSJohan Jonker - Heiko Stuebner <heiko@sntech.de> 12*32a214cdSJohan Jonker 13*32a214cdSJohan Jonkerdescription: | 14*32a214cdSJohan Jonker The RK3368 clock controller generates and supplies clocks to various 15*32a214cdSJohan Jonker controllers within the SoC and also implements a reset controller for SoC 16*32a214cdSJohan Jonker peripherals. 17*32a214cdSJohan Jonker Each clock is assigned an identifier and client nodes can use this identifier 18*32a214cdSJohan Jonker to specify the clock which they consume. All available clocks are defined as 19*32a214cdSJohan Jonker preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be 20*32a214cdSJohan Jonker used in device tree sources. Similar macros exist for the reset sources in 21*32a214cdSJohan Jonker these files. 22*32a214cdSJohan Jonker There are several clocks that are generated outside the SoC. It is expected 23*32a214cdSJohan Jonker that they are defined using standard clock bindings with following 24*32a214cdSJohan Jonker clock-output-names: 25*32a214cdSJohan Jonker - "xin24m" - crystal input - required 26*32a214cdSJohan Jonker - "xin32k" - rtc clock - optional 27*32a214cdSJohan Jonker - "ext_i2s" - external I2S clock - optional 28*32a214cdSJohan Jonker - "ext_gmac" - external GMAC clock - optional 29*32a214cdSJohan Jonker - "ext_hsadc" - external HSADC clock - optional 30*32a214cdSJohan Jonker - "ext_isp" - external ISP clock - optional 31*32a214cdSJohan Jonker - "ext_jtag" - external JTAG clock - optional 32*32a214cdSJohan Jonker - "ext_vip" - external VIP clock - optional 33*32a214cdSJohan Jonker - "usbotg_out" - output clock of the pll in the otg phy 34*32a214cdSJohan Jonker 35*32a214cdSJohan Jonkerproperties: 36*32a214cdSJohan Jonker compatible: 37*32a214cdSJohan Jonker enum: 38*32a214cdSJohan Jonker - rockchip,rk3368-cru 39*32a214cdSJohan Jonker 40*32a214cdSJohan Jonker reg: 41*32a214cdSJohan Jonker maxItems: 1 42*32a214cdSJohan Jonker 43*32a214cdSJohan Jonker "#clock-cells": 44*32a214cdSJohan Jonker const: 1 45*32a214cdSJohan Jonker 46*32a214cdSJohan Jonker "#reset-cells": 47*32a214cdSJohan Jonker const: 1 48*32a214cdSJohan Jonker 49*32a214cdSJohan Jonker clocks: 50*32a214cdSJohan Jonker maxItems: 1 51*32a214cdSJohan Jonker 52*32a214cdSJohan Jonker clock-names: 53*32a214cdSJohan Jonker const: xin24m 54*32a214cdSJohan Jonker 55*32a214cdSJohan Jonker rockchip,grf: 56*32a214cdSJohan Jonker $ref: /schemas/types.yaml#/definitions/phandle 57*32a214cdSJohan Jonker description: 58*32a214cdSJohan Jonker Phandle to the syscon managing the "general register files" (GRF), 59*32a214cdSJohan Jonker if missing pll rates are not changeable, due to the missing pll 60*32a214cdSJohan Jonker lock status. 61*32a214cdSJohan Jonker 62*32a214cdSJohan Jonkerrequired: 63*32a214cdSJohan Jonker - compatible 64*32a214cdSJohan Jonker - reg 65*32a214cdSJohan Jonker - "#clock-cells" 66*32a214cdSJohan Jonker - "#reset-cells" 67*32a214cdSJohan Jonker 68*32a214cdSJohan JonkeradditionalProperties: false 69*32a214cdSJohan Jonker 70*32a214cdSJohan Jonkerexamples: 71*32a214cdSJohan Jonker - | 72*32a214cdSJohan Jonker cru: clock-controller@ff760000 { 73*32a214cdSJohan Jonker compatible = "rockchip,rk3368-cru"; 74*32a214cdSJohan Jonker reg = <0xff760000 0x1000>; 75*32a214cdSJohan Jonker rockchip,grf = <&grf>; 76*32a214cdSJohan Jonker #clock-cells = <1>; 77*32a214cdSJohan Jonker #reset-cells = <1>; 78*32a214cdSJohan Jonker }; 79