1*d87642d7SJohan Jonker# SPDX-License-Identifier: GPL-2.0 2*d87642d7SJohan Jonker%YAML 1.2 3*d87642d7SJohan Jonker--- 4*d87642d7SJohan Jonker$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# 5*d87642d7SJohan Jonker$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d87642d7SJohan Jonker 7*d87642d7SJohan Jonkertitle: Rockchip RK3308 Clock and Reset Unit (CRU) 8*d87642d7SJohan Jonker 9*d87642d7SJohan Jonkermaintainers: 10*d87642d7SJohan Jonker - Elaine Zhang <zhangqing@rock-chips.com> 11*d87642d7SJohan Jonker - Heiko Stuebner <heiko@sntech.de> 12*d87642d7SJohan Jonker 13*d87642d7SJohan Jonkerdescription: | 14*d87642d7SJohan Jonker The RK3308 clock controller generates and supplies clocks to various 15*d87642d7SJohan Jonker controllers within the SoC and also implements a reset controller for SoC 16*d87642d7SJohan Jonker peripherals. 17*d87642d7SJohan Jonker Each clock is assigned an identifier and client nodes can use this identifier 18*d87642d7SJohan Jonker to specify the clock which they consume. All available clocks are defined as 19*d87642d7SJohan Jonker preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be 20*d87642d7SJohan Jonker used in device tree sources. Similar macros exist for the reset sources in 21*d87642d7SJohan Jonker these files. 22*d87642d7SJohan Jonker There are several clocks that are generated outside the SoC. It is expected 23*d87642d7SJohan Jonker that they are defined using standard clock bindings with following 24*d87642d7SJohan Jonker clock-output-names: 25*d87642d7SJohan Jonker - "xin24m" - crystal input - required 26*d87642d7SJohan Jonker - "xin32k" - rtc clock - optional 27*d87642d7SJohan Jonker - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", 28*d87642d7SJohan Jonker "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in", 29*d87642d7SJohan Jonker "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or 30*d87642d7SJohan Jonker SPDIF clock - optional 31*d87642d7SJohan Jonker - "mac_clkin" - external MAC clock - optional 32*d87642d7SJohan Jonker 33*d87642d7SJohan Jonkerproperties: 34*d87642d7SJohan Jonker compatible: 35*d87642d7SJohan Jonker enum: 36*d87642d7SJohan Jonker - rockchip,rk3308-cru 37*d87642d7SJohan Jonker 38*d87642d7SJohan Jonker reg: 39*d87642d7SJohan Jonker maxItems: 1 40*d87642d7SJohan Jonker 41*d87642d7SJohan Jonker "#clock-cells": 42*d87642d7SJohan Jonker const: 1 43*d87642d7SJohan Jonker 44*d87642d7SJohan Jonker "#reset-cells": 45*d87642d7SJohan Jonker const: 1 46*d87642d7SJohan Jonker 47*d87642d7SJohan Jonker clocks: 48*d87642d7SJohan Jonker maxItems: 1 49*d87642d7SJohan Jonker 50*d87642d7SJohan Jonker clock-names: 51*d87642d7SJohan Jonker const: xin24m 52*d87642d7SJohan Jonker 53*d87642d7SJohan Jonker rockchip,grf: 54*d87642d7SJohan Jonker $ref: /schemas/types.yaml#/definitions/phandle 55*d87642d7SJohan Jonker description: 56*d87642d7SJohan Jonker Phandle to the syscon managing the "general register files" (GRF), 57*d87642d7SJohan Jonker if missing pll rates are not changeable, due to the missing pll 58*d87642d7SJohan Jonker lock status. 59*d87642d7SJohan Jonker 60*d87642d7SJohan Jonkerrequired: 61*d87642d7SJohan Jonker - compatible 62*d87642d7SJohan Jonker - reg 63*d87642d7SJohan Jonker - "#clock-cells" 64*d87642d7SJohan Jonker - "#reset-cells" 65*d87642d7SJohan Jonker 66*d87642d7SJohan JonkeradditionalProperties: false 67*d87642d7SJohan Jonker 68*d87642d7SJohan Jonkerexamples: 69*d87642d7SJohan Jonker - | 70*d87642d7SJohan Jonker cru: clock-controller@ff500000 { 71*d87642d7SJohan Jonker compatible = "rockchip,rk3308-cru"; 72*d87642d7SJohan Jonker reg = <0xff500000 0x1000>; 73*d87642d7SJohan Jonker rockchip,grf = <&grf>; 74*d87642d7SJohan Jonker #clock-cells = <1>; 75*d87642d7SJohan Jonker #reset-cells = <1>; 76*d87642d7SJohan Jonker }; 77