1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12description: | 13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module 14 Standby Mode share the same register block. 15 16 They provide the following functionalities: 17 - The CPG block generates various core clocks, 18 - The Module Standby Mode block provides two functions: 19 1. Module Standby, providing a Clock Domain to control the clock supply 20 to individual SoC devices, 21 2. Reset Control, to perform a software reset of individual SoC devices. 22 23properties: 24 compatible: 25 enum: 26 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} 27 - renesas,r9a07g044-cpg # RZ/G2{L,LC} 28 - renesas,r9a07g054-cpg # RZ/V2L 29 30 reg: 31 maxItems: 1 32 33 clocks: 34 maxItems: 1 35 36 clock-names: 37 description: 38 Clock source to CPG can be either from external clock input (EXCLK) or 39 crystal oscillator (XIN/XOUT). 40 const: extal 41 42 '#clock-cells': 43 description: | 44 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 45 and a core clock reference, as defined in 46 <dt-bindings/clock/r9a07g*-cpg.h> 47 - For module clocks, the two clock specifier cells must be "CPG_MOD" and 48 a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>. 49 const: 2 50 51 '#power-domain-cells': 52 description: 53 SoC devices that are part of the CPG/Module Standby Mode Clock Domain and 54 can be power-managed through Module Standby should refer to the CPG device 55 node in their "power-domains" property, as documented by the generic PM 56 Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. 57 const: 0 58 59 '#reset-cells': 60 description: 61 The single reset specifier cell must be the module number, as defined in 62 the <dt-bindings/clock/r9a07g0*-cpg.h>. 63 const: 1 64 65required: 66 - compatible 67 - reg 68 - clocks 69 - clock-names 70 - '#clock-cells' 71 - '#power-domain-cells' 72 - '#reset-cells' 73 74additionalProperties: false 75 76examples: 77 - | 78 cpg: clock-controller@11010000 { 79 compatible = "renesas,r9a07g044-cpg"; 80 reg = <0x11010000 0x10000>; 81 clocks = <&extal_clk>; 82 clock-names = "extal"; 83 #clock-cells = <2>; 84 #power-domain-cells = <0>; 85 #reset-cells = <1>; 86 }; 87