1*f8ec8912SLad Prabhakar# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f8ec8912SLad Prabhakar%YAML 1.2 3*f8ec8912SLad Prabhakar--- 4*f8ec8912SLad Prabhakar$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" 5*f8ec8912SLad Prabhakar$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*f8ec8912SLad Prabhakar 7*f8ec8912SLad Prabhakartitle: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode 8*f8ec8912SLad Prabhakar 9*f8ec8912SLad Prabhakarmaintainers: 10*f8ec8912SLad Prabhakar - Geert Uytterhoeven <geert+renesas@glider.be> 11*f8ec8912SLad Prabhakar 12*f8ec8912SLad Prabhakardescription: | 13*f8ec8912SLad Prabhakar On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module 14*f8ec8912SLad Prabhakar Standby Mode share the same register block. 15*f8ec8912SLad Prabhakar 16*f8ec8912SLad Prabhakar They provide the following functionalities: 17*f8ec8912SLad Prabhakar - The CPG block generates various core clocks, 18*f8ec8912SLad Prabhakar - The Module Standby Mode block provides two functions: 19*f8ec8912SLad Prabhakar 1. Module Standby, providing a Clock Domain to control the clock supply 20*f8ec8912SLad Prabhakar to individual SoC devices, 21*f8ec8912SLad Prabhakar 2. Reset Control, to perform a software reset of individual SoC devices. 22*f8ec8912SLad Prabhakar 23*f8ec8912SLad Prabhakarproperties: 24*f8ec8912SLad Prabhakar compatible: 25*f8ec8912SLad Prabhakar const: renesas,r9a07g044-cpg # RZ/G2{L,LC} 26*f8ec8912SLad Prabhakar 27*f8ec8912SLad Prabhakar reg: 28*f8ec8912SLad Prabhakar maxItems: 1 29*f8ec8912SLad Prabhakar 30*f8ec8912SLad Prabhakar clocks: 31*f8ec8912SLad Prabhakar maxItems: 1 32*f8ec8912SLad Prabhakar 33*f8ec8912SLad Prabhakar clock-names: 34*f8ec8912SLad Prabhakar description: 35*f8ec8912SLad Prabhakar Clock source to CPG can be either from external clock input (EXCLK) or 36*f8ec8912SLad Prabhakar crystal oscillator (XIN/XOUT). 37*f8ec8912SLad Prabhakar const: extal 38*f8ec8912SLad Prabhakar 39*f8ec8912SLad Prabhakar '#clock-cells': 40*f8ec8912SLad Prabhakar description: | 41*f8ec8912SLad Prabhakar - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 42*f8ec8912SLad Prabhakar and a core clock reference, as defined in 43*f8ec8912SLad Prabhakar <dt-bindings/clock/r9a07g044-cpg.h> 44*f8ec8912SLad Prabhakar - For module clocks, the two clock specifier cells must be "CPG_MOD" and 45*f8ec8912SLad Prabhakar a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>. 46*f8ec8912SLad Prabhakar const: 2 47*f8ec8912SLad Prabhakar 48*f8ec8912SLad Prabhakar '#power-domain-cells': 49*f8ec8912SLad Prabhakar description: 50*f8ec8912SLad Prabhakar SoC devices that are part of the CPG/Module Standby Mode Clock Domain and 51*f8ec8912SLad Prabhakar can be power-managed through Module Standby should refer to the CPG device 52*f8ec8912SLad Prabhakar node in their "power-domains" property, as documented by the generic PM 53*f8ec8912SLad Prabhakar Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. 54*f8ec8912SLad Prabhakar const: 0 55*f8ec8912SLad Prabhakar 56*f8ec8912SLad Prabhakar '#reset-cells': 57*f8ec8912SLad Prabhakar description: 58*f8ec8912SLad Prabhakar The single reset specifier cell must be the module number, as defined in 59*f8ec8912SLad Prabhakar the <dt-bindings/clock/r9a07g044-cpg.h>. 60*f8ec8912SLad Prabhakar const: 1 61*f8ec8912SLad Prabhakar 62*f8ec8912SLad Prabhakarrequired: 63*f8ec8912SLad Prabhakar - compatible 64*f8ec8912SLad Prabhakar - reg 65*f8ec8912SLad Prabhakar - clocks 66*f8ec8912SLad Prabhakar - clock-names 67*f8ec8912SLad Prabhakar - '#clock-cells' 68*f8ec8912SLad Prabhakar - '#power-domain-cells' 69*f8ec8912SLad Prabhakar - '#reset-cells' 70*f8ec8912SLad Prabhakar 71*f8ec8912SLad PrabhakaradditionalProperties: false 72*f8ec8912SLad Prabhakar 73*f8ec8912SLad Prabhakarexamples: 74*f8ec8912SLad Prabhakar - | 75*f8ec8912SLad Prabhakar cpg: clock-controller@11010000 { 76*f8ec8912SLad Prabhakar compatible = "renesas,r9a07g044-cpg"; 77*f8ec8912SLad Prabhakar reg = <0x11010000 0x10000>; 78*f8ec8912SLad Prabhakar clocks = <&extal_clk>; 79*f8ec8912SLad Prabhakar clock-names = "extal"; 80*f8ec8912SLad Prabhakar #clock-cells = <2>; 81*f8ec8912SLad Prabhakar #power-domain-cells = <0>; 82*f8ec8912SLad Prabhakar #reset-cells = <1>; 83*f8ec8912SLad Prabhakar }; 84