1f8ec8912SLad Prabhakar# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2f8ec8912SLad Prabhakar%YAML 1.2 3f8ec8912SLad Prabhakar--- 4f8ec8912SLad Prabhakar$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" 5f8ec8912SLad Prabhakar$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6f8ec8912SLad Prabhakar 7*678eb675SBiju Dastitle: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode 8f8ec8912SLad Prabhakar 9f8ec8912SLad Prabhakarmaintainers: 10f8ec8912SLad Prabhakar - Geert Uytterhoeven <geert+renesas@glider.be> 11f8ec8912SLad Prabhakar 12f8ec8912SLad Prabhakardescription: | 13*678eb675SBiju Das On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module 14f8ec8912SLad Prabhakar Standby Mode share the same register block. 15f8ec8912SLad Prabhakar 16f8ec8912SLad Prabhakar They provide the following functionalities: 17f8ec8912SLad Prabhakar - The CPG block generates various core clocks, 18f8ec8912SLad Prabhakar - The Module Standby Mode block provides two functions: 19f8ec8912SLad Prabhakar 1. Module Standby, providing a Clock Domain to control the clock supply 20f8ec8912SLad Prabhakar to individual SoC devices, 21f8ec8912SLad Prabhakar 2. Reset Control, to perform a software reset of individual SoC devices. 22f8ec8912SLad Prabhakar 23f8ec8912SLad Prabhakarproperties: 24f8ec8912SLad Prabhakar compatible: 25*678eb675SBiju Das enum: 26*678eb675SBiju Das - renesas,r9a07g044-cpg # RZ/G2{L,LC} 27*678eb675SBiju Das - renesas,r9a07g054-cpg # RZ/V2L 28f8ec8912SLad Prabhakar 29f8ec8912SLad Prabhakar reg: 30f8ec8912SLad Prabhakar maxItems: 1 31f8ec8912SLad Prabhakar 32f8ec8912SLad Prabhakar clocks: 33f8ec8912SLad Prabhakar maxItems: 1 34f8ec8912SLad Prabhakar 35f8ec8912SLad Prabhakar clock-names: 36f8ec8912SLad Prabhakar description: 37f8ec8912SLad Prabhakar Clock source to CPG can be either from external clock input (EXCLK) or 38f8ec8912SLad Prabhakar crystal oscillator (XIN/XOUT). 39f8ec8912SLad Prabhakar const: extal 40f8ec8912SLad Prabhakar 41f8ec8912SLad Prabhakar '#clock-cells': 42f8ec8912SLad Prabhakar description: | 43f8ec8912SLad Prabhakar - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 44f8ec8912SLad Prabhakar and a core clock reference, as defined in 45*678eb675SBiju Das <dt-bindings/clock/r9a07g*-cpg.h> 46f8ec8912SLad Prabhakar - For module clocks, the two clock specifier cells must be "CPG_MOD" and 47*678eb675SBiju Das a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>. 48f8ec8912SLad Prabhakar const: 2 49f8ec8912SLad Prabhakar 50f8ec8912SLad Prabhakar '#power-domain-cells': 51f8ec8912SLad Prabhakar description: 52f8ec8912SLad Prabhakar SoC devices that are part of the CPG/Module Standby Mode Clock Domain and 53f8ec8912SLad Prabhakar can be power-managed through Module Standby should refer to the CPG device 54f8ec8912SLad Prabhakar node in their "power-domains" property, as documented by the generic PM 55f8ec8912SLad Prabhakar Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. 56f8ec8912SLad Prabhakar const: 0 57f8ec8912SLad Prabhakar 58f8ec8912SLad Prabhakar '#reset-cells': 59f8ec8912SLad Prabhakar description: 60f8ec8912SLad Prabhakar The single reset specifier cell must be the module number, as defined in 61*678eb675SBiju Das the <dt-bindings/clock/r9a07g0*-cpg.h>. 62f8ec8912SLad Prabhakar const: 1 63f8ec8912SLad Prabhakar 64f8ec8912SLad Prabhakarrequired: 65f8ec8912SLad Prabhakar - compatible 66f8ec8912SLad Prabhakar - reg 67f8ec8912SLad Prabhakar - clocks 68f8ec8912SLad Prabhakar - clock-names 69f8ec8912SLad Prabhakar - '#clock-cells' 70f8ec8912SLad Prabhakar - '#power-domain-cells' 71f8ec8912SLad Prabhakar - '#reset-cells' 72f8ec8912SLad Prabhakar 73f8ec8912SLad PrabhakaradditionalProperties: false 74f8ec8912SLad Prabhakar 75f8ec8912SLad Prabhakarexamples: 76f8ec8912SLad Prabhakar - | 77f8ec8912SLad Prabhakar cpg: clock-controller@11010000 { 78f8ec8912SLad Prabhakar compatible = "renesas,r9a07g044-cpg"; 79f8ec8912SLad Prabhakar reg = <0x11010000 0x10000>; 80f8ec8912SLad Prabhakar clocks = <&extal_clk>; 81f8ec8912SLad Prabhakar clock-names = "extal"; 82f8ec8912SLad Prabhakar #clock-cells = <2>; 83f8ec8912SLad Prabhakar #power-domain-cells = <0>; 84f8ec8912SLad Prabhakar #reset-cells = <1>; 85f8ec8912SLad Prabhakar }; 86